Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2011-07-12
2011-07-12
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
C716S117000, C716S132000
Reexamination Certificate
active
07979835
ABSTRACT:
A method of estimating resource requirements for a circuit design is disclosed. The method comprises identifying intermediate circuit modules of a netlist associated with the circuit design; accessing a library of resource requirements for intermediate circuit modules of netlists for circuit designs; selecting intermediate circuit modules of the library according to predetermined parameters for the circuit design; and generating an estimate of resource requirements for the circuit design based upon resource requirements of the selected intermediate circuit modules.
REFERENCES:
patent: 6578174 (2003-06-01), Zizzo
patent: 7028283 (2006-04-01), Keller
patent: 7058921 (2006-06-01), Hwang et al.
patent: 7165229 (2007-01-01), Gathoo et al.
patent: 7376929 (2008-05-01), Grant
patent: 7464345 (2008-12-01), Martin et al.
patent: 7631284 (2009-12-01), Perry et al.
patent: 7735050 (2010-06-01), Yu et al.
patent: 7823092 (2010-10-01), Perry
patent: 2002/0072893 (2002-06-01), Wilson
patent: 2002/0188910 (2002-12-01), Zizzo
patent: 2005/0183055 (2005-08-01), Herrera
patent: 2007/0028196 (2007-02-01), Martin et al.
patent: 2008/0134127 (2008-06-01), Allen et al.
Bilavarn et al., “Fast Prototyping of Reconfigurable Architectures from a C Program,” 2003 Int'l Symposium on Circuits and Systems, 4 pages.
Bjureus et al., “FPGA Resourcce and Timing Estimation from Matlab Execution Traces,” CODES'02, 2002 ACM, pp. 31-36.
Dutt et al., “Bridging High-Level Synthesis to RTL Technology Libraries,” 28thACM/IEEE Design Automation Conference, 1991 ACM, pp. 526-529.
Haldar et al., “A System for Synthesizing Optimized FPGA Hardware from Matlab,” 2001 IEEE, pp. 314-319.
Jha et al., “Rapid Estimation for Parameterized Components in High-Level Synthesis,” IEEE Trans. on VLSI Systems, vol. 1, No. 3, Sep. 1993, pp. 296-303.
Shankar et al., “Annotation Methods and Application Abstractions,” 2007 IEEE, 5 pages.
Shi et al., “A System Level Resource Estimation Tool for FPGAs,” 2004 Int'l Conference of Field Programmable Logic and Applications, 11 pages.
Vootukuru et al., “Partitioning of Register Level Designs for Multi-FPGA Synthesis,” pp. 99-106, no date.
U.S. Appl. No. 11/707,616, filed Feb. 16, 2007, Schumacher.
U.S. Appl. No. 12/041,150, filed Mar. 3, 2008, Schumacher et al.
U.S. Appl. No. 12/041,167, filed Mar. 3, 2008, Schumacher et al.
Kulkarni et al., “Fast Area Estimation to Support Compiler Optimizations in FPGA-based Reconfigurable Systems,”Proceedings of the 10thAnnual IEEE Symposium on Field-Programmable Custom Computing Machines(FCCM'02), Apr. 22-24, 2002, pp. 239-247, Napa, California.
Kulkarni et al., “Compile-Time Area Estimation for LUT-Based FPGAs,”ACM Transactions on Design Automation of Electronic Systems, Jan. 2006, pp. 1-19, vol. 11, No. 1.
Menn et al., “Controller Estimation for FPGA Target Architectures During High-Level Synthesis,”15thInternational Symposium on System Synthesis(ISSS'02), Oct. 2-4, 2002, pp. 56-61, Kyoto, Japan.
Milder et al., “Fast and Accurate Resource Estimation of Automatically Generated Custom DFT IP Cores,”Proceedings of the 2006 ACM/SIGDA 14thInternational Symposium on Field Programmable Gate Arrays, Feb. 22-24, 2006, pp. 211-220, Monterey, California.
Xu et al., “ChipEst-FPGA: A Tool for Chip Level area and Timing Estimation of Lookup Table Based FPGAs for High Level Applications,”Proceedings of the ASP-DAC Design Automation Conference 1997, Jan. 28-31, 1997, pp. 435-440, Chiba, Japan.
Xilinx, Inc., “CORE Generator Guide,” Version 4.1i, copyright 1991-2001, pp. 1-170, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124, USA.
Bilavarn, Sebastien et al., “Area Time Power Estimation for FPGA Based Designs at a Behavioral Level,”Proc. of the 7thIEEE International Conference on Electronics, Circuits, and Systems, Dec. 17, 2000, pp. 524-527, vol. 1, IEEE, Piscataway, New Jersey, USA.
Brandolese, Carlo et al., “An Area Estimation Methodology for FPGA Based Designs at SystemC-Level,”Proc. of the 41stAnnual Conference on Design Automation, Jun. 7, 2004, pp. 129-132, IEEE Computer Society, Washington, DC, USA.
Nayak, Anshuman et al., “Accurate Area and Delay Estimators for FPGAs,”Proc. of the IEEE Conference on Design, Automation and Test in Europe, Mar. 4, 2002, pp. 862-869, IEEE, Piscataway, New Jersey, USA.
Xu, Min et al., “Area and Timing Estimation for Lookup Table Based FPGAs,”Proc. of the 1996 European Design and Test Conference, Mar. 11, 1996, pp. 151-157, IEEE, Piscataway, New Jersey, USA.
Schumacher, Paul et al., “Fast and Accurate Resource Estimation of RTL-Based Designs Targeting FPGAS,”2008 International Conference on Field Programmable Logic and Applications(FPL'08), Sep. 8-10, 2008, pp. 59-64, Heidelberg, Germany.
Janneck Jorn W.
Jha Pradip Kumar
Miller Ian D.
Parlour David B.
Schumacher Paul R.
Cartier Lois D.
Garbowski Leigh Marie
King John J.
Xilinx , Inc.
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