Method of estimating performance of integrated circuit designs

Details Method of estimating performance of integrated circuit designs Method of estimating performance of integrated circuit designs

1999-07-21

2002-12-24

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C703S013000

Reexamination Certificate

active

06499129

ABSTRACT:

MICROFICHE APPENDIX
This application includes a microfiche appendix having 5 sheets and a total of 404 frames. This microfiche appendix contains a C++ source code listing.
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND OF THE INVENTION
The present invention relates to the field of electronic design automation (EDA) software, and more specifically, to techniques of verifying, evaluating, and estimating the performance of integrated circuits.
Integrated circuit technology is a marvel of the modem age. Integrated circuits are used in many applications such as computers, consumer electronics, networking, and telecommunications. There are many types of integrated circuits including microprocessors, microcontrollers, application specific integrated circuits (ASICs), gate arrays, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), and Flash memories. Integrated circuits are also sometimes referred to as “chips.”
Integrated circuit technology continues to rapidly advance. Automation tools are needed to simplify and expedite the task of designing an integrated circuit. It is important to be able to accurately predict or estimate the performance of an integrated circuit before the integrated circuit is fabricated. Techniques are needed to provide accurate, fast estimates of the performance of an integrated circuit.
As semiconductor processing techniques continue to improve, the performance of integrated circuits also continues to improve. Deep-submicron integrated he circuit technology has enabled commercial multimillion transistor commercial integrated circuits operating at, for example, 500 megahertz. High clock frequencies require the ability to reliably analyze the performance of circuits with little tolerance for error. A 10 percent tolerance in a performance estimate of a 500 megahertz design equates to a margin of 200 picoseconds, which is 0.200 nanoseconds. In other words, there is little room for error in performance estimation.
In addition to accuracy, capacity, and speed are also important considerations for any performance estimation technique. For example, time-to-market pressures demand performance analysis tools with the ability to obtain an accurate snapshot of the performance of a 10-million-transistor design within a day so that system architects can make meaningful architectural tradeoffs without having to wait for days to obtain an accurate result.
As can be seen, techniques are needed to predict and estimate the performance of integrated circuits, especially fast and efficient techniques that provide accurate results for integrated circuit designs with a large number of transistors.
SUMMARY OF THE INVENTION
The present invention provides a technique for the performance verification, evaluation, and estimation of integrated circuits. In an embodiment, the technique of the present invention is embodied in a computer software program that is to be executed by a computer system. In particular, the technique facilitates accurate estimates of the performance (e.g., transient delays) of an integrated circuit and has fast execution times. Although applicable to small circuits having relatively few transistors, the technique is especially suited for integrated circuits having millions of transistors and components.
The technology of the present invention is broadly applicable to custom, semicustom, and high-performance integrated circuits. The present invention may be used to accurately estimate the performance of all the paths of an integrated circuit. When used in designs operating in the 250 megahertz to 1 gigahertz range, and greater, the software of present invention can provide results within a design tolerance of about two percent.
Further, the present invention handles the complexities of integrated circuit technology, including deep-submicron effects. To achieve such tight tolerances, the performance estimation technique handles the deep-submicron effects of RC-interconnect and transistor interaction, cross-coupling capacitance, simultaneous-switching, and waveform shape. These effects are dynamic in nature and traditional techniques of static transistor-level path analysis or library-based approaches cannot incorporate these dynamic effects. The present invention provides significantly more accurate performance estimates for deep-submicron designs compared to other techniques such as static path analysis.
Since the present invention uses a dynamic simulation approach, it is able to incorporate cross-coupling capacitance, simultaneous-switching, and waveform shape effects with results that are comparable to Spice-level simulation. The present invention also produces fewer false paths with resulting savings in designer time and effort. A divide-and-conquer approach enables the present invention to deal with very large designs, with turnaround times of under a day for 10-million-transistor designs.
In an embodiment of the present invention, the performance of an integrated circuit is estimated by partitioning a netlist into strongly coupled components (SCCs). A plurality of vectors is generated for each of the strongly coupled components. Strongly driven nodes are determined for each SCC. Vector pairs are sequenced and accurate simulation is performed on each strongly coupled component. The result is an accurate estimate of the performance of the integrated circuit, covering all the paths. Moreover, strongly coupled components and the simulation results obtained during a first execution of software of the present invention are saved in a database. During subsequent executions, these saved strongly coupled components and the simulation results are reused for those strongly coupled components that are unchanged, saving considerable time.
Other aspects of the present invention include tighter integration between timing analysis and characterization by including Boolean information and automatic elimination of global (block-level) false paths.
In an embodiment, the invention is a method of evaluating the performance of an integrated circuit. A netlist or circuit description is partitioned into strongly coupled components. A number of vectors is generated for the strongly coupled components. The strongly driven nodes are determined. Stimulus is generated for the strongly coupled components. A strongly coupled component includes a first channel-connected component and a second channel-connected component. The first channel-connected component influences a Boolean output of the second channel-connected component, and the second channel-connected component influences a Boolean output of the first channel connected component. A strongly driven node includes a logical element driving the node with a drive strength greater than another logical element driving the same node.
In another embodiment, the invention is a computer program product including a computer usable medium with computer readable code for causing an evaluation of the performance of an integrated circuit. The computer program product includes computer readable code devices configured to cause a computer to effect partitioning a netlist into strongly coupled components; computer readable code devices configured to cause a computer to effect generating a plurality of vectors for the strongly coupled components; and computer readable code devices configured to cause a computer to effect determining strongly driven nodes.
The invention is further a method of estimating the performance of an integrated circuit design including selecting a circuit block of the integrate

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