Method of estimating logic cell delay time

Details Method of estimating logic cell delay time Method of estimating logic cell delay time

1990-12-05

1993-12-28

Harvey, Jack B.

Boots, shoes, and leggings

364490, G06F 1560

Patent

active

052745686

ABSTRACT:
A method for approximating the delay time of an excitation through a logic cell using the summation of a base delay, which is a function of delay coefficients for the cell and the total output load capacitance of the cell, and a rise/fall time correction, which is determined from the output rise/fall time of the driving cell and the sensitivity of the analyzed cell to rise/fall time. Other corrections/compensating factors include a performance derating factor which accounts for the multiplicative effects of operating voltage, temperature and process.

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patent: 4698760 (1987-10-01), Lembach et al.
patent: 4916388 (1990-04-01), Sano
patent: 4916627 (1990-04-01), Hathaway
patent: 5051911 (1991-09-01), Kimura et al.
patent: 5077676 (1991-12-01), Johnson et al.
patent: 5168455 (1992-12-01), Hooper

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