Method of estimating degradation with consideration of hot carri

Details Method of estimating degradation with consideration of hot carri Method of estimating degradation with consideration of hot carri

1997-12-05

2000-04-04

Hong, Stephen S.

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

714 55, 714 24, 714 37, 324769, G06F 1126

Patent

active

060472472

ABSTRACT:
There is provided a hot-carrier-delay-degradation estimation method of estimating, based on the actual operation of an LSI, deterioration in reliability thereof due to the influence of hot carriers. At a delay calculation step, there are calculated, for the cells of an LSI serving as the object of timing verification, delays, input slew and output load capacitances based on circuit information and a delay library containing delay parameters. At a delay degradation library generation step, there is generated a delay degradation library containing delay parameters at the time when the LSI has operated for a predetermined period of time. This delay degradation library is generated (i) based on the delay library and delay degradation parameters in which changes in delay of the cells due to the influence of hot carriers are expressed in terms of changes in delay parameter accompanied by the numbers of operation times of the cells and (ii) with the use of the estimated numbers of operation times, input waveform inclinations and output load capacitances of the cells. By repeating these two steps the predetermined number of repetition times, there are obtained delays of the cells at the time when the LSI has operated for a period of time equivalent to the product of the predetermined period of time and the number of repetition times.

REFERENCES:
patent: 4816753 (1989-03-01), Palkuti
patent: 5491657 (1996-02-01), Haddad et al.
patent: 5508632 (1996-04-01), Shimizu et al.
patent: 5587665 (1996-12-01), Jiang
patent: 5650938 (1997-07-01), Bootehsaz et al.
patent: 5872717 (1999-02-01), Yu et al.
J. Rubinstein, et al., "Signal Delay in RC Tree Networks", IEEE Transactions on Computer-Aided Design, vol. CAD-2, No. 3, Jul. 1983, pp. 202-211.
J. Qian, et al., "Modeling the "Effective Capacitance" for the RC Interconnect of CMOS Gates", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 12, Dec. 1994, pp. 1526-1535 .

Affiliated with

Also associated with

Rating

Method of estimating degradation with consideration of hot carri does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of estimating degradation with consideration of hot carri, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of estimating degradation with consideration of hot carri will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-373901