Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-08-02
2003-09-09
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S185030
Reexamination Certificate
active
06618297
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor nonvolatile memory integrated circuits with multi-bit memory cells, each having more than two states defined by memory cell conduction threshold voltages and read-verify conduction currents. The invention relates in particular to methods of establishing the reference voltage or current levels that demarcate the different states for use in program verify operations and memory read operations.
BACKGROUND ART
The threshold voltage characteristic of an EPROM or flash EEPROM floating gate transistor structure is controlled by the amount of charge that is retained on its floating gate. That is, the minimum (threshold) amount of voltage that must be applied to the structure's control gate before the transistor can turn “on” to permit conduction between its source and drain regions is controlled by the level of charge on the floating gate.
The floating gate of a memory cell can retain any amount of charge within a range of charges, and therefore the memory cell can be programmed to exhibit a range of threshold voltage levels for conduction and a corresponding range of conduction current levels. Each memory cell can be caused to store more than one bit of data by partitioning its programmed charge into three or more ranges. Each cell is then programmed into one of those ranges.
In order to define multiple memory states, the memory system designates threshold windows corresponding to each of those states. Memory states representing n bits of data are demarcated using 2
n
threshold windows. For example, if four ranges are used, two bits of data can be stored in a single cell. If eight ranges are used, three bits of data can be stored, 16 ranges permit storage of four data bits per cell, etc.
The amount of current flowing between a memory cell's source and drain is directly related to the threshold level of the addressed memory cell. To sense any one of these states, the control gate is raised to a read/verify gate voltage, for example V
g
=+5V, the drain is biased to 0.5V−1.0V range, and the amount of source-drain conduction current I
ds
is sensed. Current sensing amplifiers attached to bit lines of the memory cell array are capable of distinguishing between the several conduction states by comparison with a set of corresponding reference currents.
A reference circuit generates a plurality of reference voltages or reference currents corresponding to the defined memory states. The reference values may be generated from a reference cell, which can be floating gate transistors identically constructed like the memory cells and pre-programmed to the desired thresholds of conduction. Reference values used in the prior art typically coincide with the boundaries between memory states.
During programming, a sequence of programming and verify pulses continues until the sensed current drops slightly below the reference current corresponding to the desired state. The reference currents for program verify operations may be somewhat shifted by a specified margin amount to place them closer to the midpoint between the boundaries for the adjacent lower and higher states. During read operations, the programmed state of a memory cell is sensed by comparing the conduction current with each of the reference currents corresponding to the different states.
An object of the present invention is to provide an improved means for generating reference currents for memory read, program verify and erase verify operations which are self-aligning.
DISCLOSURE OF THE INVENTION
The object is met by a method and circuit generating the read and program verify reference currents for a multi-bit nonvolatile memory cell array, in which both sets of current levels are defined from a set of reference current values establishing the center of the memory cell states. For a four level memory cell with states “00”, “01”, “10” and “11”, four reference currents I
R00
, I
R01
, I
R10
and I
R11
are established by one or four programmed reference cells. In one embodiment, each of four reference cells are programmed to a different one of the four states and provide the four reference currents directly. In another embodiment a single reference cell programmed in the “11” state (the fully erased state with no floating gate charge, minimum threshold voltage and maximum read conduction current) is used to derive all four reference currents via a current mirror circuit. For cells with 8, 16 or other numbers of states, a corresponding number of reference currents are generated in analogous fashion.
For n memory states, (n−1) read current levels representing the boundaries between memory states are typically derived from the arithmetic average of the reference currents for adjacent states. Thus, a read boundary current I
i,i+1
between states i and i+1 is defined by the average of reference currents I
Ri
and I
Ri+1
, i.e.:
I
i,i+1
=(0.50)
I
Ri
+(0.50)
I
Ri+1
.
For a four state memory cell, the three read current levels I
H
, I
M
and I
L
are defined by averaging adjacent pairs of the four reference currents I
R00
, I
R01
, I
R10
and I
R11
supplied by the reference memory cells. These averages are established using the same analog circuit described below that defines the program verify current levels, but with a margin value m set at substantially 50%. However, other margin values close to, but not exactly at, 50% might be used to define the read current levels representing the boundaries between memory states. That is, the established read currents may be somewhat above or below the average value, using a margin somewhere in a preferred range of between 40% and 60%.
The program verify current levels are also generated from adjacent reference currents using an analog circuit. Upper and lower current levels for the verify window are established for most states, except that a lower current level for the fully programmed state (“00” in a four level cell) is not needed. Also, the upper and lower current levels for the fully erased state (“11” in a four level cell) is optional, and is used only for verifying over-erase recovery operations. For a memory state i, the upper and lower verify levels I
iH
and I
iL
are defined as:
I
iH
=(1
−m
)
I
Ri
+(
m
)
IR
i+1
;
and
I
iL
=(1
−m
)
I
Ri
+(
m
)
I
Ri−1
,
where m is the preset margin value for the programming operation. As there is no I
Ri+1
for i=“11”, the upper verify level I
11H
is defined as:
I
11H
=(1
+m
)
I
R11
.
The margin value m in all cases is less than 50%, and is typically between 0.05 and 0.375, with values between 0.10 and 0.25 being preferred. The margin can differ for each program verify level. A user selectable margin may be provided. Current mirrors with selectable sizes can be used to provide the (1−m)I
R
and (m)I
R
current levels to be combined.
REFERENCES:
patent: 5434825 (1995-07-01), Harari
patent: 6044019 (2000-03-01), Cernea et al.
patent: 6069821 (2000-05-01), Jun et al.
patent: 6097637 (2000-08-01), Bauer et al.
patent: 6246613 (2001-06-01), Banks
patent: 6538922 (2003-03-01), Khalid et al.
Atmel Corporation
Phung Anh
Protsik Mark
Schneck Thomas
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