Method of erasure for a non-volatile semiconductor memory device

Details Method of erasure for a non-volatile semiconductor memory device Method of erasure for a non-volatile semiconductor memory device

1993-02-19

1994-07-05

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Erase

365185, G11C 1140

Patent

active

053273850

ABSTRACT:
The invention provides a method of erasure for a non-volatile semiconductor memory device having a floating gate. For a first time interval, a voltage having one polarity is applied to a control gate of said memory device under a bias application between source and drain regions so as to accomplish an erasure by a tunneling of electrons from said floating gate through a tunneling oxide film. For a second time interval after said first time interval, a voltage having an opposite polarity to said one polarity is applied to said control gate of said memory device without bias application between said source and drain regions so as to accomplish a convergence of a threshold voltage into a voltage level by a tunneling of electrons from a channel region of said memory device to said floating gate through said tunneling oxide film.

REFERENCES:
patent: 5233562 (1993-08-01), Ong et al.
"A self-convergence Erasing Scheme For A Simple Stacked Gate Flash EEPROM", IEEE, By S. Yamada et al., pp. 307-310.
"Drain-disturb characteristic of an erased Flash EEPROM cell", 10a-SF-22, By S. Yamada et al., English translation.
"A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM", 28p-ZM-14, By T. Suzuki et al., English translation.

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