Static information storage and retrieval – Read/write circuit – Erase
Patent
1993-03-01
1994-03-15
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Erase
365185, 365900, G11C 700
Patent
active
052951073
ABSTRACT:
A method of controlling the nonvolatile memory device comprising making over-erasing simultaneously a set of EEPROM elements and then setting simultaneously the threshold voltages of said set of EEPROM elements back to the specified threshold-voltage values. The over-erasing is accomplished by applying a first pulse between the source and the control gate to induce the first FN current across the gate insulating film. The setting-back is accomplished by applying a second pulse between the well and the control gate to induce the second FN current flowing reversely to the first FN current.
REFERENCES:
patent: 4742491 (1988-05-01), Liang et al.
patent: 4884239 (1989-11-01), Ono et al.
patent: 5122985 (1992-06-01), Santin
"An In-System Reprogrammable 32K X 8 CMOS Flash Memory", Virgil Niles Kynett et al., IEEE Journal of Sold-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1157-1163.
"A Self-Convergence Erasing Scheme For A Simple Stacked Gate Flash Eeprom", Seiji Yamada et al., IEEE IEDM 91-307, 1991; pp. 11.4.1-11.4.4.
Okazawa Takeshi
Oyama Ken-Ichi
Shirai Hiroki
LaRoche Eugene R.
Mai Son
NEC Corporation
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