Method of erasing data on non-volatile semi-conductor memory

Details Method of erasing data on non-volatile semi-conductor memory Method of erasing data on non-volatile semi-conductor memory

1993-11-12

1995-05-02

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Erase

365185, 365900, G11C 700

Patent

active

054126088

ABSTRACT:
In order to suppress dispersion of threshold level voltages upon erasure of a large number of cells constituted from FETs having a floating gate electrode, drain electrode D, source electrode S and substrate Sub of each memory cell, all of the above electrodes are set to 0 V while a pulse of -19 V and a pulse width of 0.01 second is applied to control gate electrode CG to remove electrons accumulated in floating gate electrode FG by an F-N tunnel current. Then, while drain electrode D, source electrode S and substrate Sub are kept set to 0 V, another pulse of 14 V and a pulse width of 0.1 second is applied to control gate electrode CG to effect injection of electrons into floating gate electrode FG by the F-N tunnel current.

REFERENCES:
patent: 5255237 (1993-10-01), Kodama
patent: 5295107 (1994-03-01), Okazawa et al.
Seiji Yamada et al, "A Self-Convergence Erasing Scheme For a Simple Stacked Gate Flash Eeprom", Sep. 1991 IEEE, pp. 11.4.1-11.4.4.

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