Static information storage and retrieval – Read/write circuit – Erase
Patent
1992-04-10
1993-10-19
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Erase
365185, G11C 1140
Patent
active
052552373
ABSTRACT:
There is provided a method of erasing a nonvolatile semiconductor storage having a floating gate electrode with a constant threshold voltage of a memory cell transistor after an erasing operation and further with high security of superior repeat characteristics of a writing and an erasing operation and voltages free of miss-writing. On the erasing operation, a p-type semiconductor substrate is made into an earth ground, a drain is made into a floating potential and continuous pulses of negative high voltage of which parameters of multiplying pulse intervals by applying pulse numbers is 0.1 seconds or more are applied to a control gate electrode to perform intermittently the Fowler-Nordheim tunnelling of electrons from a floating gate electrode to the p-type semiconductor substrate.
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patent: 4894802 (1990-01-01), Hsia et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5132935 (1992-07-01), Ashmore, Jr.
patent: 5136541 (1992-08-01), Arauawa
1990 IEEE Symposium on VLSI Technology, R. Kirisawa et al., "A Nand Structured Cell With a New Programming Technology For Highly Reliable 5V Only Flash EEPROM", pp. 129-130, by R. Kirisawa, et al.
LaRoche Eugene R.
NEC Corporation
Nguyen Tan
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