Static information storage and retrieval – Floating gate – Particular biasing
Patent
1997-05-12
1998-08-04
Nguyen, Tan T.
Static information storage and retrieval
Floating gate
Particular biasing
36518518, G11C 1600
Patent
active
057904600
ABSTRACT:
The invention is a novel erase method for erasing flash EEPROM memory devices. A memory cell of such a memory device has a first semiconductor region of one conductivity type formed in a second region of the opposite conductivity type, source and drain regions of the opposite conductivity type formed in the first semiconductor region, and a gate. The second region is formed within a substrate of the one conductivity type. The gate includes a control gate and a floating gate, which retains charge and overlies the first semiconductor region. The erase method of the invention includes the steps of: applying a first voltage of one polarity to the source region and the first and second semiconductor regions; and simultaneously applying a second voltage of the opposite polarity to the gate, whereby any charge on the floating gate tunnels through the floating gate dielectric into both the first region and the source region, thereby removing any charge retained by the floating gate.
REFERENCES:
patent: 5243559 (1993-09-01), Murai
patent: 5361235 (1994-11-01), Kodama
patent: 5457652 (1995-10-01), Brahmbhatt
patent: 5657271 (1997-08-01), Mori
Chan I-Chuin Peter
Chen Chih-Liang
Kao Chao-Ven
Su Chien-Sheng
Yu James C.
EON Silicon Devices, Inc.
Nguyen Tan T.
LandOfFree
Method of erasing a flash EEPROM memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of erasing a flash EEPROM memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of erasing a flash EEPROM memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1185281