Fishing – trapping – and vermin destroying
Patent
1993-12-20
1995-05-30
Hearn, Brian H.
Fishing, trapping, and vermin destroying
437162, 437 46, 148DIG124, H01L 21331
Patent
active
054200504
ABSTRACT:
The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor. The method comprises the step of forming a patterned silicon dioxide layer superjacent a semiconductor substrate comprising a base, an emitter and a collector, such that a carrier current conducts between the base and the emitter. The silicon dioxide layer forms an interface on the substrate at the emitter. Further, a first polysilicon layer is formed superjacent both the patterned silicon dioxide layer and the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.
REFERENCES:
patent: 4755487 (1988-07-01), Scovell et al.
patent: 5096840 (1992-03-01), Bean et al.
patent: 5194397 (1993-03-01), Cook et al.
patent: 5238849 (1993-08-01), Sato
patent: 5296388 (1994-03-01), Kameyama et al.
Jerome Rick C.
Post Ian R. C.
Wodek Gary M.
Hearn Brian H.
Nguyen Tuan
Teitelbaum Ozer M. N.
United Technologies Corporation
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