Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization
Reexamination Certificate
2011-08-02
2011-08-02
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Optimization
C716S104000, C716S106000
Reexamination Certificate
active
07992123
ABSTRACT:
A method of engineering change to a semiconductor circuit includes: performing a first synthesis with optimization of a first HDL code to generate a first circuit; performing a first physical design of the first circuit to generate a post layout circuit; modifying the first HDL code to generate a second HDL code, and performing a second synthesis with optimization of the first and second HDL codes while forcibly preserving elements to generate a second circuit and a third circuit, respectively; performing an ECO cone-pair extraction operation of the second and third circuit to generate at least one ECO cone-pair; and obtaining an ECO logic and an element to be replaced according to the ECO cone-pair and the post layout circuit, and then replacing the element to be replaced in the post layout circuit with the ECO logic gate circuit, thereby modifying the post layout circuit into a post layout ECO circuit.
REFERENCES:
patent: 6484292 (2002-11-01), Jain
patent: 6530073 (2003-03-01), Morgan
patent: 6581199 (2003-06-01), Tanaka
patent: 2002/0162086 (2002-10-01), Morgan
patent: 2004/0025127 (2004-02-01), Takenaka
IEEE Standard Verilog Hardware Description Language, IEEE Stad 1364-2001, Sep. 28, 2001, pp. 1-791.
Dorado Design Automation, Inc.
Kirton & McConkie
Siek Vuthe
Witt Evan R.
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