Method of encapsulating a substrate-based package assembly...

Details Method of encapsulating a substrate-based package assembly... Method of encapsulating a substrate-based package assembly...

2000-12-15

2003-10-21

Ortiz, Angela (Department: 1732)

Plastic and nonmetallic article shaping or treating: processes

With severing, removing material from preform mechanically,...

Making hole or aperture in article

C264S272150, C264S272170, C264S273000, C264S274000, C264S275000, C264S276000

Reexamination Certificate

active

06635209

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated-circuit packaging technology, and more particularly, to a method of encapsulating a substrate-based package assembly without causing mold flash over exposed package surfaces.
2. Description of Related Art
Encapsulation process is an important step in integrated-circuit packaging technology, by which an epoxy-molded compound (EMC), or called an encapsulation body, is formed to encapsulate the packaged semiconductor chip for the purpose of protecting the packaged semiconductor chip against outside moisture, contamination, and damage.
One problem to the encapsulation of a substrate-based package, however, is that the encapsulation material would easily flash to the exposed package surfaces where electrical contacts are provided, thus adversely degrading the electrical coupling of those electrical contacts to external circuitry. This problem is illustratively depicted in the following with reference to
FIGS. 1A-1C
,
FIGS. 2A-2B
,
FIGS. 3A-3B
, and
FIGS. 4A-4C
, respectively for four different types of substrate-based packages.
Case 1: Wire-Bonded Single-Chip Package
FIGS. 1A-1C
are schematic sectional diagrams used to depict a conventional encapsulation method for a wire-bonded single-chip package.
Referring first to
FIG. 1A
, this wire-bonded single-chip package assembly includes: (a) a substrate
100
having a front surface
100
a
and a back surface
100
b
; (b) a semiconductor chip
110
mounted on the front surface
100
a
of the substrate
100
; (c) a first electrically-insulative layer
121
serving as a top solder mask (S/M) over the front surface
100
a
of the substrate
100
; (d) a second electrically-insulative layer
122
serving as a bottom solder mask over the back surface
100
b
of the substrate
100
; and (e) a plurality of electrical contacts
130
provided on the back surface
100
b
of the substrate
100
and electrically isolated from each other by the second electrically-insulative layer
122
.
The foregoing semi-finished package assembly is to be encapsulated through the use of a molding tool
140
composed of a bottom mold
141
having a flat top surface
141
a
and an upper mold
142
having a predefined cavity
142
a.
Referring to
FIG. 1B
, during encapsulation process, the semi-finished package assembly shown in
FIG. 1A
is fixed in the molding tool
140
in such a manner that the second electrically-insulative layer
122
on the back surface
100
b
of the substrate
100
is abutted on the flat top surface
141
a
of the bottom mold
141
. Then, an encapsulation material, such as epoxy resin, is injected into the mold cavity
142
a
(through the path indicated by the arrow M in
FIG. 1B
) to thereby form an encapsulation body
150
to encapsulate the semiconductor chip
110
and the substrate
100
.
Undesirably, however, since it would be highly difficult to make the second electrically-insulative layer
122
come into absolutely airtight abutment on the flat top surface
141
a
of the bottom mold
141
, a seam (indicated by the letter S in
FIG. 1B
) would exist between the second electrically-insulative layer
122
and the bottom mold
141
, which would allow a small amount of the encapsulation material to flash over the bottom surface of the second electrically-insulative layer
122
.
Referring further to
FIG. 1C
, as the encapsulation process is completed, the encapsulated package assembly is taken out from the molding tool
140
. As a consequence of mold flash, a mass of mold flash
150
a
would be undesirably left over the exposed bottom surface of the second electrically-insulative layer
122
and even over the electrical contacts
130
. The mold flash
150
a
would undesirably make the resulted package unit spoiled in its outer appearance and make the electrical contacts
130
unable to be reliably electrically coupled to external circuitry.
One solution to the foregoing problem of mold flash is to perform a de-flash process through the use of sanding means or laser means to remove the mold flash
150
a
. One drawback to this solution, however, is that it would easily cause damage to the substrate surfaces, thus spoiling the outer appearance of the resulted package unit.
Case 2: Wire-Bonded Stacked-Dual-Chip Package
FIGS. 2A-2B
are schematic sectional diagrams used to depict a conventional encapsulation method for a wire-bonded stacked-dual-chip package which also suffers from the problem of mold flash.
As shown in
FIG. 2A
, this wire-bonded stacked-dual-chip package assembly includes: (a) a substrate
200
having a front surface
200
a
and a back surface
200
b
; (b) a pair of stacked semiconductor chips
211
,
212
mounted on the front surface
200
a
of the substrate
200
; and (c) an electrically-insulative layer
220
serving as a solder mask (S/M) over the back surface
200
b
of the substrate
200
.
In encapsulation process, the same molding tool as the one shown in
FIGS. 1A-1B
can be used to encapsulate the foregoing semi-finished package assembly, so detailed description thereof will not be repeated herein.
As further shown in
FIG. 2B
, as the encapsulation process is completed, a mass of mold flash
250
a
would be undesirably left over the edge of the exposed back surface of the electrically-insulative layer
220
.
Case 3: Flip-Chip Package
FIGS. 3A-3B
are schematic sectional diagrams used to depict a conventional encapsulation method for a flip-chip package which also suffers from the problem of mold flash.
As shown in
FIG. 3A
, this flip-chip package assembly includes: (a) a substrate
300
having a front surface
300
a
and a back surface
300
b
; (b) a semiconductor chip
310
mounted in an upside-down (i.e., flip chip) manner on the front surface
300
a
of the substrate
300
; and (c) an electrically-insulative layer
320
serving as a solder mask (S/M) over the back surface
300
b
of the substrate
300
.
In encapsulation process, the same molding tool as the one shown in
FIGS. 1A-1B
can be used to encapsulate the foregoing semi-finished package assembly, so detailed description thereof will not be repeated herein.
As further shown in
FIG. 3B
, after the encapsulation process is completed, a mass of mold flash
350
a
would be undesirably left over the edge of the exposed back surface of the electrically-insulative layer
320
.
In the foregoing three cases, the problem of mold flash occurs on the exposed back surface of the electrically-insulative layer coated over the back surface of the substrate. However, the problem of mold flash may also occur on the front surface of the substrate, as in the case of a BGA package depicted in the following with reference to
FIGS. 4A-4C
.
Case 4: BGA-Package
FIGS. 4A-4C
are schematic sectional diagrams used to depict a conventional encapsulation method for a BGA (all Grid Array) package which also suffers from the problem of mold flash.
Referring first to
FIG. 4A
, this BGA package assembly includes: (a) a substrate
400
having a front surface
400
a
and a back surface
400
b
; (b) a semiconductor chip
410
mounted on the front surface
400
a
of the substrate
400
; (c) a first electrically-insulative layer
421
serving as a top solder mask (S/M) over the front surface
400
a
of the substrate
400
; (d) a second electrically-insulative layer
422
serving as a bottom solder mask (S/M) over the back surface
400
b
of the substrate
400
; and (e) a plurality of solder-ball pads
430
provided on the back surface
400
b
of the substrate
400
and electrically isolated from each other by the second electrically-insulative layer
422
.
The foregoing semi-finished BGA package assembly is to be encapsulated through the use of a molding tool
440
composed of a bottom mold
441
having a flat top surface
441
a
and an upper mold
442
having a predefined cavity
442
a
and a flat bottom surface
442
b.
Referring to
FIG. 4B
, during encapsulation process, the semi-finished BGA package assembly shown in
FIG. 4A
is fixed between the bottom mold
441
and the upper mold
442

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