Method of enabling timing verification of a circuit design

Details Method of enabling timing verification of a circuit design Method of enabling timing verification of a circuit design

2005-03-04

2008-08-26

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07418679

ABSTRACT:
The various embodiments of the present invention relate to circuit verification. According to one embodiment of the invention, a method of enabling timing verification of a circuit design comprises steps of generating a timing model of a processor core for a static timing analysis tool; coupling timing data related to the processor core to the static timing analysis tool; extracting resistance and capacitance data for interconnect circuits of the circuit design; coupling the resistance and capacitance data for the interconnect circuits to the static timing analysis tool; and verifying the performance of the circuit design using the static timing analysis tool. According to another embodiment of the invention, a system for enabling timing verification of a circuit design is described.

REFERENCES:
patent: 6857110 (2005-02-01), Rupp et al.
patent: 6925621 (2005-08-01), Mielke et al.

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