Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2009-04-30
2010-11-02
Smith, Zandra (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S618000, C438S623000, C438S637000, C438S642000, C257SE23021
Reexamination Certificate
active
07825022
ABSTRACT:
An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality of solder resist openings (121, 321, 521) therein. The electronic package further includes a finish layer (130, 330, 535) in the solder resist openings, an electrically conducting layer (140, 440) in the solder resist openings over the finish layer, and a solder material (150, 810) in the solder resist openings over the electrically conducting layer. The electrically conducting layer electrically connects the solder resist openings in order to enable the electrokinetic deposition of the solder material.
REFERENCES:
patent: 7413771 (2008-08-01), Arora et al.
patent: 7413805 (2008-08-01), Khaselev et al.
patent: 7678255 (2010-03-01), Khaselev et al.
Gurumurthy Charavana
Nalla Ravi
Duong Khanh B
Intel Corporation
Nelson Kenneth A.
Smith Zandra
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