Method of enabling analysis of defects of semiconductor device w

Details Method of enabling analysis of defects of semiconductor device w Method of enabling analysis of defects of semiconductor device w

1996-07-19

1999-08-31

Breneman, R. Bruce

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

216 60, 216 85, B44C 122

Patent

active

059453494

ABSTRACT:
A method of enabling analysis of defects of a semiconductor with three dimensions includes the steps of: coating a photoresist film on the passivation layer except a predetermined portion of the passivation layer including a portion where the defects exist; coating a vinyl film on the photoresist film and on the side of the wafer; removing the passivation layer on the second metal interconnect; and removing an insulating layer formed between two metal interconnects using a selective wet etching. The defects existing in the metal interconnects remaining after etching of the passivation layer and insulating layer are thereby observable, e.g., with a scanning electron microscope or equivalent, the wafer being set on a holder of the scanning electron microscope and being changed in tilt and rotational angles whereby the analysis is enabled.

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