Method of eliminating a critical mask using a blockout mask...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S258000, C438S671000

Reexamination Certificate

active

06232222

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method that reduces the use of critical masks by using a blockout mask. As a result, a unique semiconductor structure can be formed.
2. Description of the Related Art
Microelectronic circuit fabrication requires application of a series of photolithography masking steps for patterning of device structures. In advanced DRAM and logic circuits, fabrication process complexity can require more than one critical mask per level. Minimization of critical masks is critical for fabrication cost control. The present invention reduces the number of critical masks through introduction of a blockout mask. With this method, DRAM array and support contact holes can be formed in the same etching step. Similarly, logic gate conductors may be formed in the same step and later doped for a desired work function.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems of the conventional methods, it is, therefore, an object of the present invention to provide a method of forming a semiconductor structure. The method may include forming a semiconductor substrate having an array region and a support region, forming a gate stack over an array region of the semiconductor substrate and a gate stack over the support region of the substrate. Each gate stack may include a polysilicon layer and a gate cap layer. A glass layer may be formed over the gate stacks and a critical mask may be applied over the glass layer. The critical mask may have a first opening at an area corresponding to the array region and a second opening at an area corresponding to the support region. Contact holes may be formed in the glass layer at areas corresponding to the first and second opening. The critical mask may then be removed and a first blockout mask may be applied over the structure to block certain portions of the structure.
A first conductive type dopant may then be added at uncovered areas of the structure. The contact holes may be filled with polysilicon or tungsten. The structure may be annealed to spread the first conductive type dopant over the polysilicon layer. Contact holes may then be formed by etching the gate cap layer and the polysilicon layer of the array region at areas of the second opening of the critical mask.
A second blockout mask may be applied over the structure to block certain portions of the structure. A second conductive type dopant may be added at uncovered areas of the structure.
The semiconductor structure may also be formed by applying a blockout mask over the array region and the support region. The blockout mask may have at least a first opening in an area over the support region. The first opening may have a first width as measured in the first direction. A first conductive type dopant may be added into areas of the support region corresponding to the first opening of the blockout mask.
A glass layer may be formed over the gate stacks. A critical mask may be applied and have a first opening in an area of the array region and a second opening in an area of the support region. The first opening may have a second width as measured in the first direction. Contact holes may be formed in the glass layer at areas corresponding to the first opening of the critical mask and the second opening of the critical mask. The width of the contact hole in the array region may be smaller than the first width.
Other objects, advantages and salient features of the invention will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclose preferred embodiments of the invention.


REFERENCES:
patent: 4646425 (1987-03-01), Owens et al.
patent: 5111270 (1992-05-01), Tzeng
patent: 5472892 (1995-12-01), Gwen et al.
patent: 5556796 (1996-09-01), Garnett et al.
patent: 5665629 (1997-09-01), Chen et al.
patent: 6043123 (2000-03-01), Wang et al.

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