Method of electroplating copper interconnects

Details Method of electroplating copper interconnects Method of electroplating copper interconnects

1999-02-22

2001-06-12

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S677000, C438S678000, C438S759000, C205S103000, C205S104000, C205S157000, C205S220000, C205S222000

Reexamination Certificate

active

06245676

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more specifically to a method of manufacturing a semiconductor device in which flatness of the surface of an insulating film in a buried wiring formation area is ensured.
2. Description of the Related Art
In recent years, as semiconductor integrated circuits are made finer and are highly integrated, multilayering of wirings has been promoted. Under such circumstances, when a lower layer wiring is formed on a substrate interlayer insulating film formed on a semiconductor substrate and when an interlayer insulating film is deposited while covering the lower layer wiring, the surface of the interlayer insulating film formed on the lower layer wiring while covering the same is prevented from being flattened owing to a step between the ground interlayer insulating film and the lower layer wiring. Such unevenness of the interlayer insulating film formed on the lower layer wiring while covering the same prevents an upper layer wiring from being formed with high yield when the upper layer wiring is further formed on the interlayer insulating film. Accordingly, ensurance of flatness of the surface of the interlayer insulating film is important. For this, a buried wiring is formed in the interlayer insulating film to flatten the surface of the interlayer insulating film.
In the following, there will be described a method of forming a buried wiring with reference to
FIGS. 9 and 10
.
Firstly, as illustrated in FIG.
9
(
a
), an interlayer insulating film
12
comprising a silicon oxide film is formed on a silicon substrate
11
, over the entire area on which film a photoresist
13
is in turn applied to form a resist pattern corresponding to a configuration of wirings to be formed using a photolithography process, which pattern is used as a mask to form in the interlayer insulating film
12
trenches
14
-
1
,
14
-
2
,
14
-
3
, . . . ,
14
-n with about 0.5 &mgr;m depth, 0.3 to 10 &mgr;m width, and about 0.5 &mgr;m interval.
Thereafter, as illustrated in FIG.
9
(
b
), the photoresist
13
is removed, and a tantalum (Ta) barrier layer
15
is deposited on side surfaces and on a bottom surface in the trenches
14
-
1
to
14
-n and over the entire area on the interlayer insulating film
12
, and further a copper seed layer
16
is formed over the entire area on the barrier layer
15
. The deposition of the barrier layer
15
and the formation of the copper seed layer
16
are achieved respectively with a CVD method, a sputtering method, and the like, all well known. The barrier layer
15
is provided to prevent copper from diffusing into the silicon oxide film to produce a leakage current between the wirings or along a junction part in the silicon substrate.
As illustrated in FIG.
1
(
c
), with a fountain plating method where the copper seed layer
16
is used as an electrode a copper plating layer
17
is deposited, which buries the trenches
14
-
1
to
14
-n and has a substantially flat surface over a wide area on the interlayer insulating film
12
.
As illustrated in
FIG. 10
, with chemical and mechanical polishing (CMP) the entire surface of the silicon substrate
11
on which the copper plated layer
17
is formed is polished until the interlayer insulating film
12
is exposed, to leave the copper plated layer
17
only in the trenches
14
-
1
to
14
-n and hence form a buried wiring
18
.
Referring now to
FIG. 11
, there will be described the fountain plating method in the process illustrated in FIG.
9
(
c
).
FIG. 11
is a schematical view exemplarily illustrating a fountain plating apparatus.
The fountain plating apparatus
21
includes as illustrated in the same figure a substantially cylindrical plating tank
23
for temporarily storing a plating solution
22
in which copper ion (Cu
2
+) is dissolved, a cylindrical fountain cup
24
contained in the plating tank
23
, a disk-shaped fixing plate
25
comprising an insulating material horizontally disposed slightly above the fountain cup
24
, a plating solution fountaining fountain pipe
26
opened from a bottom surface of the fountain cap
24
upward at the center of the same, and a discharge pipe
27
for the plating solution
22
opened into the tank from a bottom surface of the plating tank
23
. A pump and a plating solution tank are provided (not shown) outside the plating tank
23
, and the plating solution
22
is introduced with use of the pump into the fountain cup
24
from the plating solution through the fountain pipe
26
and is returned from the plating tank
23
into the plating solution tank. The silicon substrate
11
is fixed to a lower surface
25
a
of a fixing plate
25
on which the copper plated layer
17
is to be deposited.
For forming the copper plated layer
17
on the silicon substrate
11
using the fountain plating apparatus
21
the silicon substrate
11
is first fixed to the lower surface
25
a
of the fixing plate
25
, and then the fixing plate
25
to which the silicon substrate
11
is fixed is disposed horizontally at a predetermined position slightly above the plating solution
22
, actuating the pump (not shown) to fountain the plating solution
22
from the fountain pipe
26
. In this state, there is applied predetermined voltage where a fountain cup
24
side is set to be positive (+) and a silicon substrate
11
(copper seed layer
16
) side is set to be negative (−) to conduct a current, and then a liquid level of the plating solution
22
is raised to fountain the plating solution
22
onto the surface of the silicon substrate
11
as indicated by an arrow whereby the copper plated layer
17
is deposited on the copper seed layer
16
.
The plating solution
22
which has completed the deposition of the copper plated layer
17
overflows from an upper part of the fountain cup
24
to the side of the same. After the elapse of a predetermined time, the fountaining of the plating solution
22
is interrupted to lower the liquid level, and the fixing plate
25
is removed from the plating tank
23
and the silicon substrate
11
is removed from the silicon substrate
11
. In such a manner, there is ensured the silicon substrate
11
where the copper plating tank
17
is deposited at a predetermined position. Although the aforementioned fountain plating apparatus
21
is an example where the fountain cup
24
is used as the positive electrode, another apparatus may be used in which a mesh electrode is provided in the fountain cup
24
to which positive voltage is applied, and in which the fountain cup
24
itself is not used as an electrode.
Although in the above description the fountain cup
24
side is set positive with the silicon substrate
11
side set negative, and predetermined voltage is applied thereacross to conduct a current, as described in Japanese Patent Laid-Open Application No. Sho57-71150, 1st to 7th lines on a left lower column, p.230, a plating speed at high current density is high in the fountain plating method so that no flat copper plated layer
17
is obtained when a fixed pattern current is conducted at all times.
To solve the problem there is known a plating solution (hereinafter, referred to a retarding agent) which is adsorbed at high current density portions on an exposed surface of the metal seed layer
16
or the copper plated layer
17
and into which there is added an additive that prevents copper from adhering to such portions (CubathM: trade name of ENTHONE OMI company, for example).
When a plating solution
22
containing such a retarding agent is used, the plating speed is slowed down automatically at high current density portions, so that a current having a unidirectional polarity at all times ensures a plated layer having a substantially flat surface. Accordingly, as illustrated in FIGS.
12
(
a
) and (
b
), a negative DC current or negative DC pulsed current both having a unidirectional polarity is conducted to achieve fountain plating and hence ensure a copper plated layer
17
having a

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