Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-02-22
2003-03-04
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06528424
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor devices and their methods of fabrication. More particularly, the present invention relates to the processing of copper interconnect material and the resultant device utilizing the same. Even more particularly, the present invention relates to reducing electromigration in copper interconnect lines by doping their surfaces with a barrier material using wet chemical methods.
BACKGROUND ART
Currently, the semiconductor industry is demanding faster and denser devices (e.g., 0.05-&mgr;m to 0.25-&mgr;m) which implies an ongoing need for low resistance metallization. Such need has sparked research into resistance reduction through the use of barrier metals, stacks, and refractory metals. Despite aluminum's (Al) adequate resistance, other Al properties render it less desirable as a candidate for these higher density devices, especially with respect to its deposition into plug regions having a high aspect ratio cross-sectional area. Thus, research into the use of copper as an interconnect material has been revisited, copper being advantageous as a superior electrical conductor, providing better wettability, providing adequate electromigration resistance, and permitting lower depositional temperatures. The copper (Cu) interconnect material may be deposited by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, electroless plating, and electrolytic plating.
However, some disadvantages of using Cu as an interconnect material include etching problems, corrosion, and diffusion into silicon.
1
These problems have instigated further research into the formulation of barrier materials for preventing electromigration in both Al and Cu interconnect lines. In response to electromigration concerns relating to the fabrication of semiconductor devices particularly having aluminum-copper alloy interconnect lines, the industry has been investigating the use of various barrier materials such as titanium-tungsten (TiW) and titanium nitride (TiN) layers as well as refractory metals such as titanum (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), and their silicides.
2
Although the foregoing materials are adequate for Al interconnects and Al—Cu alloy interconnects, they have not been entirely effective with respect to all-Cu interconnects. Further, though CVD and PECVD have been conventionally used for depositing secondary metal(s) on a primary metal interconnect surface, neither technique provides a cost-effective method of forming a copper-zinc alloy on a Cu interconnect surface. Therefore, a need exists for a low cost and high throughput method of forming by electroplating a uniform Cu-rich copper-zinc alloy (Cu—Zn) thin film on a improves interconnect reliability, enhances electromigration resistance, and improves corrosion resistance.
1
Peter Van Zant, Microchip Fabrication: A Practical Guide to Semiconductor Processing, 3
rd
Ed., p. 397 (1997).
2
Id., at 392.
DISCLOSURE OF INVENTION
Accordingly, the present invention provides a method for forming, by electroplating, a Cu-rich (e.g., ≦90 at. % Cu) Cu—Zn alloy thin film on a Cu surface by electroplating the Cu surface in a unique nontoxic aqueous chemical electroplating solution containing salts of zinc (Zn) and copper (Cu), their complexing agents, a pH adjuster, and surfactants; and a semiconductor device thereby formed. The present invention further provides a particular electroplating method which controls the parameters of Zn concentration, pH, temperature, and time in order to form a uniform Cu-rich copper-zinc alloy (Cu—Zn) thin film on a cathode-wafer surface such as a copper (Cu) surface for reducing electromigration in the device by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate.
More specifically, the present invention provides a method for fabricating a semiconductor device having a Cu—Zn alloy thin film formed on a Cu surface, acting as cathode-wafer surface, by electroplating the Cu surface in the present chemical solution. The method generally comprises the steps of: (1) providing a semiconductor substrate having a Cu surface; (2) providing a chemical solution; (3) electroplating the Cu surface in the chemical solution, thereby forming the Cu—Zn.alloy thin film on the Cu surface; (4) rinsing the Cu—Zn alloy thin film; (5) drying the Cu—Zn alloy thin film; and (6) completing fabrication of the semiconductor device.
By electroplating this Cu—Zn alloy thin film on the cathode-wafer surface using a stable chemical solution in the prescribed concentration ranges, the present invention improves Cu interconnect reliability, enhances electromigration resistance, improves corrosion resistance, and reduces manufacturing costs. In particular, the present invention chemical solution is advantageous in that it facilitates formation of an acceptable Cu—Zn alloy thin film over a wide range of bath compositions. The desirable Zn concentration in the Cu—Zn alloy thin film, preferably in a range of approximately 0.2 at. % to approximately 9.0 at. % determined by X-Ray Photoelectron Spectroscopy (XPS) or Auger Electron Spectroscopy (AES), is controllable by varying the electroplating conditions and/or the bath composition.
These advantages arise from the present invention's superior fill-characteristics.
The present Cu—Zn electroplating solution facilitates better filling of a Cu—Zn alloy thin film on an interconnect, especially for feature sizes in a dimensional range of approximately 0.2 &mgr;m to approximately 0.05 &mgr;m, thereby lowering the resistance of the formed Cu—Zn alloy thin film (e.g., in a resistance range of approximately 2.2 &mgr;&OHgr;·cm to approximately 2.5 &mgr;&OHgr;cm for approximately 1 at. % Zn content in a Cu—Zn alloy thin film, as deposited). Further, the filling capability is enhanced by three beneficial characteristics of the present invention: (1) the instant chemical solution does not etch copper or a copper alloy seed layer; (2) the introduction of Zn into the alloy thin film as well as onto the Cu interconnect improves both step coverage and nucleation; and (3) a variety of organic additives, such as polyethylene glycol (PEG), organo-disulfides, and organo-chlorides, are compatible and may be included in the instant chemical solution for further enhancing the fill profile and grain structure. The present Cu—Zn electroplating solution provides a desirably low Zn content in a Cu alloy interconnect (e.g., in a concentration range of approximately 0.2 at. % to approximately 1.0 at. %) which also imparts (1) a de minimis increase in resistance as well as (2) a maximum improvement in electromigration resistance. The present chemical solution can also provides a desirably low Zn content (e.g., in a range of<<approximately 0.1 at. % or<<approximately 0.2 at. %, virtually undetectable by AES) in a Cu film, wherein the Zn content may be engineered by varying the deposition parameters as well as by modifying the bath composition.
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Peter Van Zant, “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, 3rdEd., p. 392 and 397 (1997).
A. Krishnamoorthy, D. Duquette and S. Murarka, “Electrochemical Codeposition and Electrical Characterization of a Copper-Zinc Alloy Metallization”, in edited by Adricacos, et al., Electrochem Society Symposium Proceedings, vol. 99-9, May 3-6, Seattle, p. 212.
J. Cunningham, “Using Electrochemistry to Improve Copper Interconnect”, in Semiconductor International, Spring 2000 (May).
L. Chen and T. Ritzdorf, “ECD Seed Layer for Inlaid Copper Metallization” in edited by Andricacos, et al., Electrochem Society Proceedings, vol. 99-9, May 3-6, Seattle, p. 122.
Lopatin Sergey
Nickel Alexander H.
Advanced Micro Devices , Inc.
Isaac Stanetta
LaRiviere Grubman & Payne, LLP
Niebling John F.
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