Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
1998-12-03
2001-09-11
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C324S713000
Reexamination Certificate
active
06288556
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a lithographic technique and more specifically to a method of electrically measuring misregistration used in measuring misregistration errors.
Conventionally, the misregistration of exposure processes for fabricating semiconductor devices is measured in terms of electrical resistance values of a pattern for measuring the amount of misregistration.
For example, in the paper entitled “Automatic Testing and Analysis of Misregistrations Found in Semiconductor Processing” by I. J. STEMP, K. H. NICHOLAS, and H. E. BLOCKMAN, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-26. No. 4, pp. 729 to 732, April 1979, it is concluded that the misregistration measurement precision is 20 nm and this precision will suffice.
However, taking into consideration the design of recent semiconductor devices, the measurement precision needs to be at least 5 nm. For semiconductor devices of the future, the measurement precision will need to be 1 nm. Therefore, there is a need for some idea that allows for measurements at precision higher than the present level.
The aforementioned technique expects an improvement in measurement precision through resistance measurement based on four-point measurements; however, no four-point measurement is actually used and no measurement pattern is presented.
Due to the aberration of the projection optical system, the pattern will shift its transferred location according to its density level. In the aforementioned technique, an isolated pattern is used to measure an amount of misregistration and its density differs from that of an actual device pattern. For this reason, the measured value will not be trustworthy.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of electrically measuring misregistration in a semiconductor device which allows a measurement to be made at the same density as in an actual device pattern and the level of registration of actual patterns to be measured with higher precision.
According to an aspect of the present invention there is provided a method of electrically measuring misregistration of patterns comprising a first step of forming a first-level measurement pattern and then forming a second-level measurement pattern on the first-level measurement pattern, a second step of measuring electrical resistance between terminals provided in either the first-level measurement pattern or the second level measurement pattern, and a third step of calculating an amount of misregistration between the first-level measurement pattern and the second-level measurement pattern from the measured resistance value, characterized in that in the first step, at least one of the first-level measurement pattern and the second-level measurement pattern is formed so that it has at least two pattern elements.
According to another aspect of the present invention there is provided a method of measuring misregistration of patterns comprising: a first step of a first-level measurement pattern; a second step of forming a second-level measurement pattern on the first-level measurement pattern; a third step of measuring electrical resistance between terminals provided in either the first-level measurement pattern or the second-level measurement pattern; and a fourth step of calculating an amount of misregistration between the first-level measurement pattern and the second-level measurement pattern from the measured electrical resistance, and wherein in the first or second step, at least one of the first-level measurement pattern and the second-level measurement pattern is formed so that it has at least two pattern elements, and each of the measurement patterns has separate patterns for displacement in the plus direction and displacement in the minus direction.
According to sill another aspect of the present invention there is provided a method of electrically measuring misregistration of patterns comprising a first step of forming a first-level measurement pattern and then forming a second-level measurement pattern on the first-level measurement pattern, a second step of measuring electrical resistance between terminals provided in either the first-level measurement pattern or the second level measurement pattern, and a third step of calculating an amount of misregistration between the first-level measurement pattern and the second-level measurement pattern from the measured resistance value, characterized in that in the first step, at least one of the first-level measurement pattern and the second-level measurement pattern is formed so that it has at least two pattern elements, and the second-level measurement pattern is divided in the lengthwise direction of the first-level measurement pattern into a main pattern element and subpattern elements.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
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Ivor J. Stemp et al. “Automatic Testing and Analysis of Misregsitrations Found in Semiconductor Processing” Transactions on Electronic Devices, vol. 26, No. 4, pp. 729-732, Apr. 1997.
Junichiro Iba et al. “Electrical Characterization of Across-Field Lithographic Performance for 256 bit DRAM Technologies” SPIE vol. 2512, pp. 218-225, Apr. 1995.
M. W. Cresswell et al. “Electrical Test Structure for Overlay Metrology Referenced to Absolute Length Standards” SPIE vol. 2196, pp. 512-521, 1994, No month available.
Asanuma Keita
Higashiki Tatsuhiko
Iba Junichiro
Nomura Hiroshi
Ozaki Toru
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Metjahic Safet
Nguyen Vincent Q.
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