Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-05-18
2002-08-20
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S042000, C714S746000, C714S768000, C711S106000, C711S113000
Reexamination Certificate
active
06438726
ABSTRACT:
TECHNICAL FIELD
The present invention relates to error correction of data in a memory device, and more particularly, to a method of dual use of memory for error correction in a non-volatile memory device.
BACKGROUND ART
In semiconductor integrated memory devices, such as non-volatile memory devices, errors sometimes occur when data are written to or read from the memory devices. Sometimes errors in data storage may occur due to the physical characteristics of the memory devices. For example, in a conventional flash memory device, errors in the data stored in the flash memory may be caused by manufacturing defects or program disturbances. A program disturbance may be caused by an undesirable field turn-on in a typical conventional flash memory array during the programming of the memory gates in the conventional flash memory array. A field turn-on in the substrate region under the select gate transistor field oxide region between two memory gates on adjacent bit lines may cause one of the memory gates which is supposed to be in a program-inhibited state indicating a logic bit “1” to be “turned on” to a programmed state indicating a logic bit “0”. Bit errors in the data stored in a conventional non-volatile memory device may also be caused by various other factors.
In order to provide an acceptable level of reliability of data read from a conventional flash memory array, error correcting codes have been integrated into memory storage systems to correct bit errors in the data stored in the memory. Conventional error correcting codes such as block codes have been used in the error correction of data in conventional memory storage systems. For example, Hamming codes, which are within a class of conventional block codes well known to a person skilled in the art, have been used to provide single-bit error correction to preserve the accuracy of data in conventional memory storage devices.
Error checking and correction of data read from a flash memory array cause a delay from the time the data are pre-read from the memory by an error correction circuit to the time the error correction circuit enables the corrected data to be accessed externally by a host system. In order to minimize the time delay, error correction circuits have been implemented to compute the error addresses, that is, the syndrome generated by the error correcting block code, by parallel processing of the data read from the memory device. However, conventional error correction circuits with parallel processing capabilities can be very expensive to implement because of the complexity of the hardware. Parallel processing of data in the computation of the error addresses requires a large number of logic gates. For example, for every 1,000 bits of data read from the conventional flash memory device, approximately 5,000 XOR gates may be required for the parallel processing of data to minimize the delay in computing the syndrome.
Some applications may require that the cost of the memory storage system be minimized rather than the delay from the time of pre-reading the data from the memory array by the error correction circuit to the time the error correction circuit enables the corrected data to be read externally. In order to minimize the hardware cost, conventional error correction circuits and the methods have been implemented which involve serial processing of the data stored in the memory array to generate error addresses based upon a conventional error correcting block code. However, conventional serial processing may require hundreds of clock cycles of delay in the data access time before the data are read by the host system. A long time delay caused by the serial processing of the data may be unacceptable in some applications.
Therefore, there is a need for an error correction circuit and a method of error correction which are capable of reducing the cost of the hardware required for computing the error addresses compared to the hardware costs associated with the conventional parallel processing of the data read from the memory device, while reducing the data access time delay compared to the relatively long time delays resulting from the conventional serial processing of the data to generate the error addresses. Furthermore, there is a need for a method of allocating data words and error correction bytes in a page of memory to allow for efficient error correction of the data while reducing the hardware cost.
DISCLOSURE OF THE INVENTION
The present invention satisfies these needs. In accordance with the present invention, a method of dual use of memory for error correction in a memory device generally comprises the steps of:
(a) dividing a memory page into a first portion and a second portion;
(b) assigning data to the first portion of the memory page; and
(c) assigning a plurality of error correction bytes to the second portion of the memory page.
In an embodiment in which the first portion, that is, the data portion of the memory page comprises 512 bytes of data, the first portion of the memory page is divided into 20 data words comprising a first data word and 19 additional data words, the first data word comprising 18 bytes of data and each of the nineteen additional data words comprising 26 bytes of data. The error correction bytes assigned to the second portion of the memory page may comprise error correction bytes each capable of providing error correction for a respective one of the twenty data words. The total amount of memory in the memory page is thus 532 bytes, comprising 512 data bytes and 20 error correction bytes.
In an embodiment in which the first portion of the memory page is capable of storing a plurality of data words including a first data word and at least one additional data word subsequent in sequence to the first data word, the length of the additional data word may be greater than that of the first data word but less than twice that of the first data word. By assigning less number of data bytes to the first data word than the number of data bytes in each of the additional data words, the error correction process can be expedited by processing two data words simultaneously.
The method of dual use of memory for error correction in accordance with the present invention is applicable to the error correction of data bytes in both reading and writing operations. In an embodiment which is applicable to the reading operation of a memory array, the method according to the present invention further comprises the steps of:
(d) pre-reading the first and second data words, each of the data words comprising a plurality of bytes identified by a plurality of corresponding data word byte addresses, comprising the steps of:
(i) pre-reading the second data word when the first data word is being read;
(ii) coding each of the data words to generate a respective code word; and
(iii) counting the bytes of each of the data words to generate a plurality of byte ordinals for the bytes in each of the data words;
(e) generating a syndrome for each of the data words based upon the code words and the even and odd bytes of the byte ordinals, the syndrome comprising a byte error address and a bit error address;
(f) comparing the data word byte address with the byte error address to determine whether the data word byte address matches the byte error address;
(g) generating an error correction enable signal in response to a determination by the step of comparing the data word byte address with the byte error address that the data word byte address matches the byte error address;
(h) decoding the bit error address to generate a decoded bit error address for each of the data words; and
(j) generating an error corrected byte for each of the data words based upon the decoded bit error address in response to the error correction enable signal.
When the memory array operates in an error correction mode, the error correction bytes are assigned to the second portion of the memory page, whereas the first portion of the memory page is allocated for the storage of data bytes. In the embodiment in which the first portion comprises 512
Fliesler Dubb Meyer & Lovejoy LLP
Moise Emmanuel L.
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