Method of dual masking for selective gap fill of submicron inter

Details Method of dual masking for selective gap fill of submicron inter Method of dual masking for selective gap fill of submicron inter

1996-02-26

1998-08-04

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438669, 438778, 438763, 438780, H01L 2144

Patent

active

057893195

ABSTRACT:
A semiconductor device and method having a low-permittivity material between closely-spaced leads in order to decrease unwanted capacitance, while having a more structurally strong dielectric between widely-spaced leads where capacitance is not as critical. A metal layer 14 is deposited on a substrate 12 of a semiconductor wafer 10, where the metal layer 14 has a first region 15 and a second region 17. An insulating layer 39 is deposited on the metal layer, and the insulating layer 39 is patterned with a conductor pattern of widely-spaced leads and closely-spaced leads. Widely-spaced leads 16 are formed in the first region 15 of the metal layer 14. At least adjacent portions of closely-spaced leads 18 are formed in the second region 17 of the metal layer 14. A low-permittivity material 34 is deposited between adjacent portions of the closely-spaced leads 18. A structural dielectric layer 26 is deposited between at least the widely-spaced leads. The low-permittivity material 34 is a material with a dielectric constant of less than 3. An advantage of the invention includes improved structural strength by placing structurally weak low-permittivity material only where needed, in areas having closely-spaced leads.

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