Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-04-24
2004-08-17
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220
Reexamination Certificate
active
06778442
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the field of non-volatile memory devices and, more particularly, to a method of storing data using a flash memory device, such as a dual cell, charge trapping dielectric, electrically erasable and programmable memory device.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated circuit memory unit, such as a flash memory unit. Memory units often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual cell memory device, such as a charge trapping dielectric flash memory device, can store data in a “double-bit” arrangement. That is, one bit (i.e., a binary data value have two states, such as a logical one and a logical zero) can be stored using a charge storing cell on a first “side” of the memory device and a second bit can be stored using a complimentary charge storing cell on a second “side” of the memory device.
Programming of such a memory device can be accomplished, for example, by hot electron injection. Hot electron injection involves “pulsing” the device by applying appropriate voltage potentials to each of a gate and a drain of the memory device for a specified duration. During the programming pulse, the source is typically grounded. Reading of the memory device can be accomplished by applying an appropriate voltage to each of the gate and the drain and comparing the drain to source current (as an indication of device threshold voltage) against a reference value to determine if the read charge trapping cell is in a programmed or an unprogrammed state.
Even though conventional charge trapping dielectric flash memory devices are capable of storing two single-bit binary data values per memory device, conventional charge trapping dielectric flash memory devices can suffer from data retention problems, especially over repeated program/erase (P/E) cycles. The causes of data retention problems can include charge loss and complimentary bit disturb (e.g., when a programmed side of the memory device effects the threshold voltage of the memory device during reading of an unprogrammed side of the memory device).
As a result, there is an ever increasing demand to store data in memory devices while increasing the data retention ability and reliability characteristics of the memory devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is directed to a method of programming a charge trapping dielectric memory device having a first charge storing cell and a second charge storing cell. The method can include over-erasing the first and second charge storing cells to shift an erase state threshold voltage of the memory device to be lower than a natural state threshold voltage; programming the first charge storing cell to store a first amount of charge corresponding to a first program state selected from a blank program level and a first charged program level; and programming the second charge storing cell to store a second amount of charge corresponding to a second program state selected from the blank program level and a second charged program level.
According to another aspect of the invention, the invention is directed to a method of programming a charge trapping dielectric memory device having a first charge storing cell and a second charge storing cell. The method can includes programming the first charge storing cell to store a first amount of charge corresponding to a charged program level; programming the second charge storing cell to store a second amount of charge corresponding to the charged program level; and verifying that the second programmed charge storing cell stores charge corresponding to the charged program level and if the verification fails, re-pulsing each of the first programmed charge storing cell and the second programmed charge storing cell.
According to yet another aspect of the invention, the invention is directed to a method of programming a charge trapping dielectric memory device having a first charge storing cell and a second charge storing cell. The method can includes programming the first charge storing cell to store a first amount of charge corresponding to a charged program level; programming the second charge storing cell to store a second amount of charge corresponding to the charged program level; and verifying that the first programmed charge storing cell stores charge corresponding to the charged program level and if the verification fails, re-pulsing each of the first programmed charge storing cell and the second programmed charge storing cell.
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Hamilton Darlene G.
Hsia Edward
Lee Mimi
Madhani Alykhan
Tanpairoj Kulachet
Advanced Micro Devices , Inc.
Renner , Otto, Boisselle & Sklar, LLP
Tran M.
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