Method of driving ferroelectric gate transistor memory cell

Details Method of driving ferroelectric gate transistor memory cell Method of driving ferroelectric gate transistor memory cell

1995-03-14

1997-09-09

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Ferroelectric

257295, G11C 1122

Patent

active

056663056

ABSTRACT:
A ferroelectric gate transistor has a structure in which n-type source and drain regions are formed on a p-type semiconductor, a ferroelectric thin film is formed on a channel region between the source and drain regions, and a gate electrode is formed thereon. Memory information is erased by applying a voltage V.sub.g to the ferroelectric to cause poling in the first direction. The memory information is written by applying a voltage V.sub.W lower than a coercive voltage of the ferroelectric and having a polarity opposite to that of the voltage V.sub.g to the ferroelectric. The memory information is read out by applying a voltage V.sub.DR lower than the voltage V.sub.W and having a polarity opposite to that of the voltage V.sub.g to the drain to read a drain current I.sub.DS.

REFERENCES:
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patent: 5307305 (1994-04-01), Takasu
patent: 5412596 (1995-05-01), Hoshiba
Science, Dec. 15, 1989, vol. 246, No. 4936, James F. Scott et al; "Ferroelectric Memories", pp. 1400-1405, American Association for the Advancement of Science.
Kyoyudentai Hakumaku Shyusekika Gijutsu, "Ferroelectric Thin Film Integration Technique", Chapter 5, Section 3, Science Forum Publishing Co. 1992, pp. 261-274.
3rd International Symposium on Integrated Ferroelectrics, Apr. 3-5, 1991, Takashi Mihara et al, pp. 116-137, "Process Dependent Electrical Characteristics . . . ".

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