Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-04-26
2003-12-02
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S620000, C438S637000
Reexamination Certificate
active
06656833
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices, and more specifically to a method of fabricating a semiconductor device in which lower and upper contact plugs are aligned with each other and directly connected.
2. Description of the Related Art
Dynamic random access memories are used in many applications because of their space savings feature. This is achieved by their memory cells requiring only one capacitor for holding a single bit of information and one transistor as a switching gate for read/write operation. Recent technology for dynamic random access memories is toward further reducing the space of their capacitor by fabricating it in a layered structure, known as stacked capacitors. The stacked capacitors are of two types, the fin type and the cylinder type. Stacked capacitors of the cylinder type are particularly suited for memories of 4 megabits or more that are integrated in LSI chips. Due to their cylindrical structures, memories of desired capacitance can be obtained simply by increasing their vertical dimension. However, this results in an increased thickness of insulation between upper and lower layers which must be interconnected, and hence a lengthened inter-layer connection. To form an inter-layer connection, one approach is to etch a one-length hole through the insulation and fill the hole with a contact plug. This technique requires a long time to provide etching through the full length of insulation. If an intermediate layer is additionally provided between the upper and lower layers and a throughhole must be etched to the intermediate layer concurrently with the etching of the interconnection throughhole, over-etching occurs on the intermediate layer. To avoid this problem, it is the usual practice to use two contact plugs, one on the intermediate layer and the other beneath it and connect these plugs via the intermediate layer.
However, the use of the intermediate layer as an intermediary contact point between upper and lower layers often results in an increase in total length of the interconnection and hence an increase in resistance and in propagation delay. This is undesirable where high speed operation is important. Although this problem may be eliminated by vertically aligning upper and lower contact plugs and connecting them together with via an intermediate layer, it is still necessary to provide a sufficient space for purposes of insulation between such an intermediate layer and other intermediate layers.
In addition, there is still a need to create a direct interconnection between the upper and lower layer for purposes of large scale integration and high speed operation. Direct interconnection requires precision alignment of the upper contact plug with the lower contact plug. If misalignment occurs during the etching process of the upper insulation layer to create a hole above the lower contact plug, voids can occur around the upper edges of the lower contact plug due to different rates at which the lower insulation layer and the lower contact plug are tended to be etched after the hole has reached the upper end of the lower contact plug because of the need to provide over-etching of an intermediate wiring (aluminum) layer concurrently performed with the etching of the upper insulation layer. This is particularly true due to the large difference between the etch rate of insulating material and that of aluminum. The occurrence of such voids is problematic. When the upper contact hole is metallized, waste products are trapped in the voids and act as a potential source of erosion or separation of contact plugs. If the lower insulation layer is excessively etched during the formation of a misaligned upper contact hole, a void would occur that extends down to a substantial depth in the lower insulating layer and the material entrapped in such a void would create a short-circuit with an adjacent conductive layer.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of fabricating a semiconductor device free from voids which would otherwise occur when an upper contact hole is formed on a lower contact plug.
According to a first aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising the steps of forming a first insulating layer, forming an etch stopper and a first contact plug in the first insulating layer so that the etch stopper surrounds an end portion of the first contact plug, the first contact plug extending through the first insulating layer between opposite surfaces thereof, forming a second insulating layer on the first insulating layer, selectively etching the second insulating layer to form a throughhole extending to the end portion of the first contact plug, and forming a second contact plug in the throughhole.
According to a second aspect, the present invention provides a method of fabricating a semiconductor device, comprising the steps of forming a first insulating layer, forming a first contact plug in the first insulating layer, etching the first insulating layer until an end portion of the first contact plug is exposed to the outside, forming an etch stop layer on the first insulating layer so that the exposed portion of the first contact plug is embedded in the etch stop layer, anisotropically etching the etch stop layer so that a portion of the etch stop layer which surrounds the end portion of the first contact plug remains and the first insulating layer is exposed to the outside, forming a second insulating layer on the exposed first insulating layer so that the end portion of the first contact plug and the surrounding etch stop layer portion are embedded in the second insulating layer, polishing the second insulating layer until the end portion of the first contact plug, the surrounding portion of the etch stop layer and the second insulating layer present a flattened surface and the surrounding portion of the etch stop layer attains a desired width, forming a third insulating layer on the flattened surface, selectively etching the third layer to form a throughhole extending to the first contact plug, and forming a second contact plug in the throughhole.
According to a third aspect, the present invention provides a method of fabricating a semiconductor device, comprising the steps of forming a first insulating layer, forming an etch stop layer in the first layer, selectively etching an inner portion of the etch stop layer to form a throughhole in the first insulating layer so that an outer portion of the etch stop layer remains and surrounds an end portion of the throughhole, forming a first contact plug in the throughhole, polishing the first insulating layer until an end portion of the first contact plug, the outer portion of the etch stop layer and the first insulating layer form a flattened surface, forming a second insulating layer on the flattened surface, selectively etching the second insulating layer to form a throughhole extending to the first contact plug, and forming a second contact plug in the throughhole.
According to a third aspect, the present invention provides a semiconductor device comprising a lower insulating layer, a first contact plug extending across opposite surfaces of the lower insulating layer, an etch stopper surrounding an end portion of the first contact plug, an upper insulating layer on the lower insulating layer, and a second contact plug in the upper insulating layer, the second contact plug extending from the end portion of the first contact plug to an upper surface of the upper insulating layer.
According to a fourth aspect, the present invention provides a semiconductor memory device comprising peripheral circuitry formed on a first area of a substrate and an array of memory cells formed on a second area of the substrate. The peripheral circuitry comprises a lower insulating layer on the substrate, an upper insulating layer on the lower insulating layer, a wiring layer on the upper insulating layer, and a lower contact plug i
Dickstein Shapiro Morin & Oshinsky LLP.
NEC Corporation
Pham Long
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