Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-10-04
2002-11-12
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S691000, C438S698000, C438S720000, C438S687000, C438S660000, C438S652000, C438S637000, C438S643000
Reexamination Certificate
active
06479389
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
It is a general object of the present invention to provide a new and improved method of forming an integrated circuit in which special copper alloy films are formed by a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) or electro-chemical deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper corrosion/oxidation and electromigration resistant alloys.
As a background to the current invention, the requirement of lower resistance material has been more stringent as the device dimensions approach micron and sub-micron design ground rules. Pure copper metal lines have been one of the best choices because of copper's low resistivity and high conductivity. However, pure copper films are easily oxidized. Alloying copper with other elements, such as, Zr, Al, Ti, Sn, Zn, Mg aides in preventing copper oxidation/corrosion, by forming a dense passivating oxide on the copper surface. Furthermore, alloying of copper will improve the electromigration (EM) resistance of copper, due to a reduction in grain boundary diffusion.
This invention describes the formation of special copper alloy films by using a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) or electro-chemical deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper corrosion/oxidation and electromigration resistant alloys.
2. Description of Related Art
The present invention is a new and improved method for fabricating special copper alloy films by using a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) or electro-chemical deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper corrosion/oxidation and electromigration resistant alloys. High conductivity, low resistivity conducting metal lines are important in fabricating quarter micron and below semiconductor devices. The related Prior Art background patents will now be described in this section.
U.S. Pat. No. 5,891,804 entitled “Process for Conductors with Selective Deposition”, granted Apr. 6, 1999 to Havemann and Stuitz shows a copper seed layer and a copper layer there over. This is a method of forming a conductor on an interlevel dielectric layer which is over an electronic microcircuit substrate, and the structure produced thereby. The method utilizes: forming an interlevel dielectric layer over the interlevel dielectric layer; forming a conductor groove in the intralevel dielectric layer exposing a portion of the interlevel dielectric layer; anisotropically depositing a selective deposition initiator onto the intralevel dielectric layer and onto the exposed portion of the interlevel dielectric layer; and selectively depositing conductor metal to fill the groove to at least half-full. The selective deposition initiator may be selected from the group consisting of tungsten, titanium, palladium, platinum, copper, aluminum, and combinations thereof. In one embodiment, the selective deposition initiator is palladium, and the selectively deposited conductor metal is principally copper.
U.S. Pat. No. 5,891,802 entitled “Method for Fabricating a Metallization Stack Structure of Improve Electromigration Resistance and Keep Low Resistivity of ULSI Interconnects” granted Apr. 6, 1999 to Tao and Fang shows a pure copper layer sandwiched between two doped copper layers. There is described a metallization stack structure and a method for fabricating the same so as to produce a higher electromigration resistance and yet maintain a relatively low resistivity. The metallization stack structure includes a pure copper layer sandwiched between a top thin doped copper layer and a bottom thin doped copper layer. The top and bottom thin doped copper layers produce a higher electromigration resistance. The pure copper layer produces a relatively low resistivity. Note, doped copper layers increase line resistance and therefore must be thin contributing only a small cross-section of the conducting line.
U.S. Pat. No. 5,719,447 entitled “Metal Alloy Interconnections for Integrated Circuits” granted Feb. 17, 1998 to Gardner shows a barrier layer, and a physical vapor deposited (PVD) sputtered copper alloy layer. The metal-alloy interconnects of this invention comprise a substantial portion of either copper or silver alloyed with a small amount of an additive having a low residual resistivity and solid solubility in either silver or copper such that the resultant electrical resistivity is less than 3 micro-Ohm-cm
The present invention is directed to a novel and improved method of fabrication an integrated circuit, in which special copper alloy films are formed by a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) or electro-chemical deposition (ECD) techniques. The methods of the present invention make efficient use of several process steps resulting in less processing time, lower costs and higher device reliability. By said techniques, high aspect ratio vias and trenches can be filled with copper corrosion/oxidation and electromigration resistant alloys.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a new and improved method of forming an integrated circuit in which special copper alloy films are formed by combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) or electro-chemical deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper corrosion/oxidation and electromigration resistant alloys.
Prior Art methods provide the following consisting of: a semiconductor silicon substrate with the first level of metal copper wiring being defined, embedded in the first layer of insulator, silicon oxide SiO
x
. The invention starts with these conventional layers being provided by Prior Art methods, in addition, to patterned and etched via holes and trenches (channels) in deposited insulating material. Also provided by Prior Art methods, can be a metal “seed layer” and metal diffusion barrier layer beneath the metal copper wiring layers. To obtain adequate liner coverage using collimated reactive sputtered, physical vapor deposition (PVD), TaN, Ti/TiN, TiN, WN liners (diffusion barrier) and seed layers, a larger liner thickness must be applied.
Copper alloys have been found to be of advantage in the prevention of oxidation of copper and improving electromigration (EM) resistance of copper films. However, the primary method of forming copper alloys is by physical vapor deposition (PVD), a sputtering method which uses a sputtering target composed of the copper alloy. The copper films deposited from PVD methods have poor conformality and are not applicable for good planar gap fill properties. However, chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of pure copper can fill high aspect ratio vias and trenches. Note, for chemical vapor deposition (CVD) or electro-chemical deposition (ECD), only pure copper films can be deposited. This invention describes two new methods to form copper alloy films, copper alloying with, e.g., Zr, Al, Ti, Sn, Zn, Mg.
In the first embodiment of this invention physical vapor deposition (PVD) or sputtering of a copper alloy film, i.e., Zr, Al, Ti, Sn, Zn, Mg, is then followed by a chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a layer of pure copper.
In the second embodiment of this invention chemical vapor deposition (CVD) or electro-chemical deposition (ECD) deposits a layer of pure copper, which is then followed by physical vapor deposition (PVD) or sputtering of a copper alloy film, e.g., doped with Zr, Al, Ti, Sn, Zn, Mg.
In yet another embodiment to these methods, special, separate annealing steps follow said methods to enhance copper alloy formation. By the two deposition techniques briefly described above, high aspect ratio vias and trenches can be filled with coppe
Chen Sheng Hsiang
Tsai Ming-Hsing
Ackerman Stephen B
Goudreau George
Saile George O.
Taiwan Semiconductor Manufacturing Company
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