Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-09-09
2003-04-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06546543
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of displaying, inspecting and modifying pattern data for exposing with a charged particle beam.
2. Description of the Related Art
Exposure data are processed for correction in order to obtain a drawing pattern with high precision by irradiating an exposure object such as a resist-coated wafer, resist-coated mask or the like with a charged particle beam, for example, an electron beam on. In a large scale memory or a logic LSI, since a calculation time for correction of a proximity effect on exposure data is very long, approximate calculation has been adopted. In order to obtain a drawing pattern within error tolerance, exposure simulation has been performed prior to an actual exposure, and in the simulation, a drawing pattern is evaluated after exposure and based on the evaluation result, exposure simulation conditions are changed or CAD pattern data of a polygonal type are modified. Since such procedure is repeated, an LSI development period is long.
Accordingly, it has been required that exposure data before or after correction are inspected and modified in a shIrt time and the inspection and modification are not repeated or are repeated in a reduced number of times.
To be more concrete, there are following problems in the past:
(1) When exposure simulation is performed all over a chip, a calculation grid (points for calculating exposure intensity) is generated all over the chip and a result is displayed on a screen, while pattern data is read. Hence, there are a necessity for tremendous processing time and resources such as an immense memory capacity, which makes it almost impossible to verify all patterns by a delivery date.
Further, when exposure simulation is performed in a designated area on a chip, a calculation grid, as shown in
FIG. 52
, is generated in an edge region along a side of a pattern in the designated area and therefore, there is a case where it consumes several hours for the processing.
(2) Since no display function for a pattern area density is available, there is no way to quickly find out a site where correction is required.
(3) A result of exposure simulation in the designated area is displayed only in an exposure image as shown in FIG.
53
. The exposure image is displayed with exposure intensities, for example, in 20 colors in the calculation grid regions.
Exposure images can be displayed only in designated areas since a calculation time is tremendously long and for this reason, judgment on whether or not all chip area is good in patterning is solely dependent on evaluation of an exposure result.
Further, in order to attain a predictive value of a pattern width and an error thereof, an operator has to sense both edges and computes them, and especially, there is difficulty measuring a comparatively large pattern width which extends from one end to the other end on a screen.
(4) When a stencil mask is used, a block pattern arrangement on a chip is recognized in the following manner in the prior art. That is, a wafer exposing pattern, as shown in
FIG. 54
, in which a block pattern data on a stencil mask are expanded is displayed on a screen and when a position in a screen is designated by a mouse, only a block pattern available at the designated position, if any, is displayed in a different color in such a way as shown in FIG.
55
. Further, since block pattern data are expanded, only information on a designated block pattern as shown in
FIG. 56
is displayed. In
FIG. 56
, X and Y are coordinates of the origin and PDC is a code to identify a block pattern on a stencil mask.
It is accordingly not easy to quickly grasp how block pat terns are arranged on a chip.
Further, in order to display block patterns on a chip in a corresponding manner to block patterns on a stencil mask, the stencil mask has to be displayed on another graphic display apparatus and thereby correspondence between both cannot quickly be investigated with ease.
(5) No apparatus for pre-exposure inspection dedicated to block pattern data on a stencil mask is available in the prior art.
For example, since exposure of a block pattern is effected by one shot, a coulomb effect cannot be neglected when a current of one shot is much. However, in a prior art, wafer exposing data including a block pattern is all expanded and exposure simulation is performed while neglecting the coulomb effect. Hence, the precision in exposure simulation is lowered, which is a cause for the above-described repetition of processing.
Further, since, in the prior art, blanking of a block pattern, a proximity effect and a coulomb effect in a block pattern cannot be inspected prior to exposure, there is no means but to inspect them in evaluation of an exposure result.
(6) Since a drawing precision of a block pattern is higher at a position closer to the center of a stencil mask, it is necessary to change (move) a layout of a block pattern according to a drawing precision requirement.
Further, since a group of fine patterns can be subjected to exposure by one shot with use of a stencil mask, the stencil mask can enjoy a high throughput. However, since a stencil mask can be used only on a basis of one mask for one batch operation, there arises a necessity of that a block pattern on a stencil mask is restored to a group of variable-shaped patterns or, on the contrary, a group of variable-shaped patterns is changed to a block pattern, in consideration of drawing precision and throughput.
In such a case, since, in a prior art, block pattern extracting criteria given to a computer are changed and block extracting process is again performed on a CAD pattern of a polygonal type, the above described changes cannot be performed under deliberate judgment of an experienced designer with ease.
(7) While a calculation equation used in exposure simulation can be changed only before each processing in repetition based on the evaluation of a previous exposure result, this is a cause for repetition of processing of this kind.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a method of displaying, inspecting and modifying a pattern for exposure, in which exposure data before and after correction can effectively be inspected and modified, and by which an integrated circuit development period can be shortened.
In the first aspect of the present invention, as shown in
FIGS. 5
,
14
and
15
for example, there is provided a method of inspecting object exposing pattern decomposed into basic patterns, displaying a result of the inspection, and modifying the exposure pattern based on the displayed result of the inspection, the inspecting comprising the steps of: creating a first calculation candidate point between end points of a first non-contact part of a side of one of the basic patterns, the non-contact part being defined as not in contact to a side of any of the basic patterns; creating a second calculation candidate point between end points of a second non-contact part of an opposite side with the first non-contact part, the second calculation candidate point corresponding to the first calculation candidate point; creating a plurality of calculation points on a straight line passing through the first and second calculation candidate points, the calculation points being located in each traversing part of the first and second non-contact parts; calculating an exposure intensity at each calculation point; obtaining a predictive value of a drawing pattern width based on the calculation result: and calculating an error of the predictive value from a target value as the inspection result.
With the first aspect of the present invention, sufficient information on an estimated error of a drawing pattern on an object can be obtained in a shorter time.
Further, because of the shorter time, for example, exposure simulation can be performed over all chip area, which contributes to reduction in integrated circuit development period.
In the second aspect of the present invention, as shown in
FIG. 17
for example,
Hoshino Hiromi
Manabe Yasuo
Liu Andrea
Staas & Halsely LLP
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