Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-09-20
2005-09-20
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06948149
ABSTRACT:
From a plurality of overlay targets formed with patterns on a test wafer, subsets are formed and for each overlay target contained in the subsets, the measurement results of overlay shifts are obtained. Mean shifts, residual data and ranges are calculated for each subset and compared with the 100% full field results. The subset that represents the full field results to highest agreement is selected and used to measure the overlay of a second or any further wafer. A most preferred embodiment relates to selecting each of the subsets in a form such that the overlay target positions are concentric about the wafer center. In a further advantageous aspect, each of the subsets is confined to concentric areas about the wafer center, e.g., an inner circle and/or one or more outer rings. A distribution of selected overlay targets placed in representative regions on the wafer is thus guaranteed.
REFERENCES:
patent: 5521036 (1996-05-01), Iwamoto et al.
patent: 5877861 (1999-03-01), Ausschnitt et al.
patent: 6664121 (2003-12-01), Grodnensky et al.
patent: 6699624 (2004-03-01), Niu et al.
patent: 6734971 (2004-05-01), Smith et al.
Edell Shapiro & Finnan LLC
Infineon - Technologies AG
Levin Naum
Siek Vuthe
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