Method of determining the cause of open-via failures in an integ

Details Method of determining the cause of open-via failures in an integ Method of determining the cause of open-via failures in an integ

1991-07-23

1993-05-25

Anderson, Bruce C.

Radiant energy

Inspection of solids or liquids by charged particles

Methods

H01J 3700

Patent

active

052142833

ABSTRACT:
A method of analyzing an integrated circuit to determine the cause of an open or resistive intermetal via is disclosed. Instead of conventional cross-sectioning of the suspected via, the method removes the upper of the metal layers at the location of the via, with a selective etch to maintain the presence of the contaminant or other cause of failure at the via. When an isotropic metal etch is used, as is preferred, partial removal of the interlevel dielectric layer will facilitate subsequent analysis by increasing the area to be analyzed. Optical microscopy, SEM microscopy, Auger spectroscopy, EDS spectroscopy, and other conventional analysis techniques may be used at the portion of the circuit within the failed via, to indicate the composition of the undesired contaminant.

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patent: 5035768 (1991-07-01), Mu et al.
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Chen, et al., "Planarized Aluminum Metallization for Sub-0.5 .mu.m CMOS IEDM " Digest of Technical Papers, paper 3.4.1 (IEEE, Dec. 1990), pp. 51-54.
Lee, et al., "A Selective CVD Tungsten Local Interconnect Technology", IEDM Digest of Technical Papers, (IEEE, Dec. 1988), pp. 450-453.
Ono, et al., "Development of Planarized Al-Si Contact Filling Technology", VMIC Conference (IEEE, Jun. 12-13, 1990), pp. 76-81.

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