Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-06-17
2001-10-02
Beausoleil, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S725000, C714S819000, C324S076410
Reexamination Certificate
active
06298453
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to reconfigurable systems. More particularly, this invention relates to configuring a reconfigurable system having defective resources to obtain the correct operation of the system in spite of the defective resources in the system.
2. Description of the Related Art
A reconfigurable system typically refers to digital hardware having a relatively large number of programmable wire interconnections and/or gates. These programmable wire interconnections and gates are collectively referred to as resources below. The reconfigurable system can be programmed and reprogrammed to implement various logic designs. Examples of such reconfigurable systems are field programmable gate arrays (FPGAs), crossbar switches, and systems having FPGAs and/or crossbar switches.
Because of their reprogrammable nature, the reconfigurable systems can be used to design and test (i.e., prototype) logic devices. This allows the designer or manufacturer of the logic devices to find out if the logic design of a desired logic device contains any mistake without actually building the desired logic device. In addition, this allows changes in the logic design to be made relatively easily and conveniently during the design process. Once the logic design implemented in a reconfigurable system is completed and tested, if the manufacturer desires to produce the logic device in large quantities, the prototyped logic design can then be converted into an actual circuit layout to mass produce the logic device.
As the technology of fabricating semiconductor integrated circuit advances, the integration density of the reconfigurable logic system increases accordingly. In addition, the integration density of a reconfigurable logic system can be further increased by combining multiple FPGA chips to form a multi-chip module (MCM). Use of large scale integrated circuits in a reconfigurable logic system typically produces various advantages such as the enhancement of the function of the reconfigurable system and the reduction in the size and weight thereof.
However, disadvantages are also associated with the use of the large scale integrated circuits in a reconfigurable system. One disadvantage is that the large scale integration typically makes the reconfigurable system prone to defects during fabrication, thus increasing the manufacturing cost of the system. Although large and reliable systems can be manufactured by imposing extreme quality control measures and manufacturing tolerances, these measures greatly increase the manufacturing cost of the systems. On the other hand, if a device or system is found to include a defective element that cannot be repaired or replaced, the device typically becomes non-functional and must be rejected although the vast majority of elements are non-defective. This also increases the manufacturing cost of the device because it reduces the yield of the device.
One reason that the prior reconfigurable systems do not allow defects is that it is typically extremely difficult and costly to detect and locate defects in a large reconfigurable logic system to small circuit elements such as gates, wires, transistors, and crossbar switches although the reconfigurable logic system can be configured in many different ways to implement a given logic design (i.e., user design) so as to avoid all the defects in the system. This is because it is typically not possible to test arbitrary points inside an integrated circuit. The prior testing techniques for conventional digital systems only locate defects to the level of an integrated circuit chip or a replaceable unit or block within an integrated circuit. They typically are not able to locate the defects to small structures or circuit elements such as gates, wires, transistors, and crossbar switches. In addition, a test of one resource of the reconfigurable system typically requires other resources of the reconfigurable system that are known to be good or non-defective.
Thus, it is desirable to identify and avoid all of the defects of a reconfigurable logic system (i.e., to provide a defect-tolerant reconfigurable system) when configuring the reconfigurable system to implement a user design. In addition, it is also desirable to allow detection of the defects to small structures or circuit elements in the reconfigurable system in an efficient and cost-effective manner such that the reconfigurable system can be used as a defect-tolerant reconfigurable system.
SUMMARY OF THE INVENTION
One of the features of the present invention is to provide a defect-tolerant reconfigurable system, thus reducing the fabrication cost of the system.
Another feature of the present invention is to allow configuration of a reconfigurable system having defects without replacing, repairing, or removing the defects from the system.
A further feature of the present invention is to precisely locate a defect to a small circuit structure in a reconfigurable system to maximize the number of good circuit structures that can be used.
A still further feature of the present invention is to locate a defect in a reconfigurable system in an efficient and cost-effective manner.
Described below is an arrangement for configuring a reconfigurable system having a plurality of resources. The arrangement includes a compiler that configures the resources to implement a functional system in accordance with a user design. A defect database is also provided that (1) stores information indicating which of the resources is defective when the resources contain at least one defective resource, and (2) supplies the information to the compiler such that the compiler does not use the defective resource when the compiler configures the resources to implement the functional system.
In addition, a defect detection arrangement is provided to detect the defective resources among all the resources. The detection arrangement configures the resources into a number of test systems, each having a number of resources. The detection arrangement then tests and determines if each of the test systems is operational. Each resource within each of the operational test systems is then identified as non-defective. The detection arrangement then reconfigures the resources into a number of different test systems (i.e., combining different groups of resources into test systems each time) and repeats the process until substantially every one of the resources except the defective resource has been identified as non-defective.
If a test system is tested to be non-operational, then none of the resources within the test system is marked or identified as non-defective (i.e., good). Those resources remain in the assumed defective state or unknown state.
Because of the redundant testing, it is possible for some test groups to fail but all of the resources within those failed test groups are marked good. In order to locate the defective resources in such test groups, the arrangement locates (1) a first test group that is tested non-operational and (2) a second test group that is tested non-operational. The first test group has a first number of the resources and the second test group has a second number of the resources. The arrangement then determines which of the first and second numbers of the resources is a shared resource by the first and second test groups. The shared resource is then identified as defective.
Other features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
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Culbertson W. Bruce
Kuekes Philip J.
Baderman Scott
Beausoleil Robert
Hewlett--Packard Company
Li Thomas X.
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