Method of determining integrity of a gate dielectric

Details Method of determining integrity of a gate dielectric Method of determining integrity of a gate dielectric

2001-04-25

2003-06-24

Nguyen, Vinh P. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S762010

Reexamination Certificate

active

06583641

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Filed of Invention
The present invention relates generally to semiconductor and more specifically to a gate dielectric breakdown test method.
2. Description of Related Art
Dielectric breakdown is one of the main reliability concerns in Ultra Large Scale Integration (ULSI) semiconductor devices. In other words, the longer the life-time of the dielectric integrity, the better the reliability of the semiconductor device. Dielectric breakdown is generally believed to be caused by the positive charge build-up in the oxide near the injecting, cathode interface. In oxide thickness greater than 120 Å, the source of these positive charges is traditionally believed to be due to impact ionization deep within the oxide caused by the tunneling electrons. Initially, the tunneling currents are extremely low. Positive charges drift back toward the cathode and are believed to be trapped at localized weak spots. These trapped positive charges lower the energy band and lead to further electron injection. The process leads to further impact ionization and positive charge trapping, resulting in a runaway process. The final high current I injected at localized spots at positive-trapping sites produces an I
2
R heating sufficient to melt the SiO
2
. Before the catastrophic oxide rupture, oxide becomes leaky, and the leakage currents could cause circuits to be nonfunctional.
One method for determining dielectric reliability is based on an accelerated life-time stress conditions such as high gate voltage to accelerate the mechanism of breakdown from many years, under normal operating conditions, to seconds. The higher the gate voltage, the lower is time-to-breakdown. This method is well known in the art and it is called voltage ramping dielectric breakdown (VRDB) test method. The gate voltage has the strongest effect in accelerating the breakdown mechanism. However, one problem with this test method is it can offer a reliable result for dielectric structure of thickness more than 5 m, where a hard breakdown can be easily detected. But for ultra-thin gate dielectrics, below about 5 nm, the relationship between breakdown voltage and applied voltage is linear (on a logarithmic time, linear voltage scale) up to an upper limit of gate voltage, beyond which the relationship is non-linear.
This relationship is shown in
FIG. 1
for a 4.5 nm oxide. To make accurate projections of the time-to-breakdown it is highly desirable to keep the accelerated stress voltage in the range where the relationship between voltage and time-to-breakdown is linear on a logarithmic scale. In
FIG. 1
, the breakdown deviates from a linear relationship with the gate voltage at approximately 5.8 volts. This deviation puts an upper limit on the stress voltage and, therefore, a lower limit on the time required to reach breakdown.
The problem with this conventional procedure is that the only variable available in stressing the semiconductor device is the gate voltage. The gate voltage directly determines the magnitude of gate current and the gate current (or the injected charge) has a major effect on the process of dielectric degradation leading to breakdown. A higher gate current (or injected charge) requires a lower time-to-breakdown. The problem with this stress procedure is that the gate current is not controlled independently, but rather is dictated by the applied gate voltage. Thus, the required stress time cannot be decreased below a certain time limit without compromising the accuracy of the reliability projections. It will be understood by those skilled in the art that when measuring the integrity of a gate dielectric with thickness down to 16 Å, the problems would be even more serious.
FIG. 2
, shows a typical schematic of a gate dielectric breakdown VRDB test method, an n-type field effect transistor or NFET
120
comprises a substrate
100
having a diffused source region
104
, a diffused drain region
106
, and a gate oxide region or dielectric
102
. Overlying the gate oxide region is a gate electrode
110
. The gate electrode
110
is connected to a +Vg potential reference; the drain region
106
is connected to a Vd potential reference; the source region
104
is connected to a Vs potential reference; and the substrate
100
is connected to a Vsub potential reference. V.sub.S, V.sub.D and V.sub.SUB are at ground potential. In this conventional system, only Vg controls the gate dielectric voltage and the amount of current injected into the gate (with the channel inverted and source and drain grounded). Because only Vg controls the gate electric field and the gate current Jg, high values of Vg are required to reach dielectric breakdown in a reasonable time.
In a method disclosed in U.S. Pat. No. 4,382,229, issued May 3, 1983, Cottrell et al. teach that, when gate electrode
110
is biased above the threshold voltage of the NEET
120
and Vd is biased above the source voltage Vs, a channel is created between the source
104
and drain
106
and electrons flow through the channel from the source
104
to the drain
106
. Electrons flowing from the source
104
to the drain
106
are “heated” by the high electric field near the drain
106
, and a small fraction attain enough energy to surmount the energy barrier at the oxide-silicon interface and pass into the silicon oxide layer. The fraction of electrons which is emitted depends strongly on the electric field near the drain
106
and thus on the bias conditions and the device structure.
Cottrell et al. further teach that, by measuring the rate of change in gate current, the time required to achieve a predetermined change in source-to-drain current may be found. The problem with the Cottrell et al. method is that the emission current into the gate is small and applying the method to determine the time-to-breakdown of the dielectric is quite limited. Cottrell et al. teach a method for evaluating channel hot carriers in an FET, and do not address evaluation of dielectric breakdown in an FET.
In another disclosure, U.S. Pat. No. 5,615,377 issued Mar. 25, 1997 to Shimizu et al., a method of simulating hot carrier deterioration of a p-type metal-oxide semiconductor (PMOS) FET is taught. Shimitzu et al. provide a method by which a PMOS FET is forward and reverse biased. By measuring the characteristics of the PMOS FET and applying them in a simulation, Shimizu et al. estimate the deterioration of the transistor. Their teachings are limited: the method applies only to a PMOS FET and does not teach how to measure the time-to-breakdown of a PMOS FET or an NMOS FET.
In yet another disclosure, U.K. Patent Application No. 2,296,778 A, published on Oct. 7, 1996, there is disclosed a method for testing the reliability of a dielectric film on a semiconductor substrate. The method applies a gate current which is increased in successive steps until the dielectric film breaks down. A disadvantage of this method is that, in order to increase the gate current, the gate voltage must also be increased. Gate current cannot be independently controlled from gate voltage.
The method also does not work in ultra-thin dielectrics, because a very high stress field must be applied until breakdown occurs. Applying a high electric field to the gate results in inaccuracies in determining the dielectric reliability. At high electric fields the relationship between applied gate voltage and the time-to-breakdown is non-linear on a logarithmic scale, thereby causing errors in extrapolating the results to determine the time-to-breakdown.
Another method is taught by H. Ning et al. in Journal of Applied Physics, Volume 48, page 286 (1977). A negative, or reverse bias is applied to Vsub and a positive, or forward bias, is applied to Vg with Vs and Vd both at a ground potential (refer to FIG.
3
). A tungsten light bulb (not shown) supplies photons into the gate electrode
20
and gate dielectric
102
, which in turn generates electron-hole pairs in substrate
14
. The electrons gain energy from the electric field, as they drift toward the interface between the subs

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