Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2008-05-06
2008-05-06
Coleman, W. David (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S797000, C257SE23001
Reexamination Certificate
active
11523961
ABSTRACT:
A method of detecting misalignment of ion implantation areas comprises forming at least one standard pattern consisting of a first area and a second area for use in measuring resistance, implanting first and second conduction type impurity ions into the first and second areas, respectively, and measuring a resistance of the standard pattern. The method also includes forming a misalignment inspection pattern consisting of a first area and a second area on a predetermined area within a semiconductor substrate, implanting first and second conduction type impurity ions into the misalignment inspection pattern and active regions on the semiconductor substrate, respectively, and measuring a resistance of the misalignment inspection pattern. The method concludes by comparing the resistance of the standard pattern with the resistance of the misalignment inspection pattern.
REFERENCES:
patent: 5082792 (1992-01-01), Pasch et al.
patent: 5256577 (1993-10-01), Pluntke et al.
patent: 5434089 (1995-07-01), Barthez
patent: 5956566 (1999-09-01), Lin et al.
patent: 6072192 (2000-06-01), Fulford, Jr. et al.
patent: 6232619 (2001-05-01), Chen et al.
patent: 6620526 (2003-09-01), Tseng
patent: 6636313 (2003-10-01), Chen et al.
patent: 6657203 (2003-12-01), Koike
patent: 6713883 (2004-03-01), Hong et al.
patent: 6828647 (2004-12-01), Schafbauer et al.
patent: 2002/0190252 (2002-12-01), Adams et al.
Tenko Echigoya; Method for Detection of Positioning of Mask; Patent Abstracts of Japan; Publication No. 2003-059818; Publication Date: Feb. 28, 2003.
Akira Imai and Makoto Yoshida; Preparation of Pattern Data, and Production of Solid Element; Patent Abstracts of Japan; Publication No. 2000-292905; Publication Date: Oct. 20, 2000.
Hisao Takeda; Manufacture of Semiconductor Integrated Circuit Device; Patent Abstracts of Japan; Publication No. 06-267878; Publication Date: Sep. 22, 1994.
Coleman W. David
Dongbu Electronics Co. Ltd.
Fortney Andrew D.
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