Etching a substrate: processes – Nongaseous phase etching of substrate – With measuring – testing – or inspecting
Reexamination Certificate
1999-12-06
2002-01-29
Lund, Jeffrie R. (Department: 1763)
Etching a substrate: processes
Nongaseous phase etching of substrate
With measuring, testing, or inspecting
C216S085000, C216S088000, C216S022000, C216S089000, C438S008000, C438S692000, C438S007000, C438S693000
Reexamination Certificate
active
06342166
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a method of detecting an end point of chemical-mechanical polishing (CMP) of a wafer, and further to an apparatus for detecting an end point of polishing of a wafer with which the method is embodied, in which a permalloy magnetic layer or a metal layer for a device is formed on a surface of a substrate made of silicon, an alumina-titanium carbide alloy, LCD glass, an electric circuit made of Cu, Ag or Au is provided if necessary, and the wafer on which an insulating layer has been formed is chemimechanically polished.
2. Description of the Related Art
The CMP has been developed for providing smooth topographies on surfaces deposited on semiconductor substrates.
A method of CMP has been employed as follows. A wafer “w” is bonded to a plate of a holder with wax so as to be pressed against a platen to which a polishing cloth has been bonded. While supplying polishing-material slurry to the platen, the platen and the wafer are rotated to polish an insulating layer or metal layer by chemimechanically polishing the wafer until the permalloy layer or the metal layer for a device is exposed to the outside.
Another method has been employed as follows. A wafer is vacuum-adsorbed to a chuck table, and then a platen to which a polishing cloth has been bonded on the plate of a head is pressed from the upper surface of the wafer. While supplying polishing-material slurry to the upper surface of the wafer, the platen and the wafer are rotated to polish the insulating layer or metal layer by the chemimechanically polishing (CMP) the wafer until the permalloy layer or the metal layer for a device is exposed to the outside.
In the CMP process, the overall surface of the permalloy layer or the metal layer for a device is coated with copper, aluminum, silver or gold. Then, an excess portion of the metal is chemimechanically polished to obtain a device wafer having an electric circuit made of copper, aluminum, silver or gold. In another CMP process, the overall surface of the permalloy layer or the metal layer is coated with an insulating layer made of silicon oxide, aluminum oxide or titanium oxide. Then, an excess portion of the insulating layer is chemimechanically polished so that a flat wafer is obtained in which the insulating layer is mixed with the device.
FIG. 10
shows a multilayer circuit structure formed on a silicon wafer “w” having a MOSFET (refer to Japanese Patent Laid-Open No. 10-303152 and GB2324750A). On a surface of a silicon oxide insulating layer
101
a
of a polished silicon substrate
101
, the multilayer circuit includes: (1) a tungsten (W) contact plug portion
102
for connecting the MOSFET to an upper-layer circuit; (2) an aluminum local circuit portion
103
for establishing the electric connection in the CMOS circuit block; and (3) a copper global circuit portion
104
in which copper is embedded in an organic film having a low dielectric constant.
The device isolation among the MOSFET of the foregoing device wafer is performed by a CMP method to be a flattening device isolating structure in which the silicon oxide films are embedded in grooves formed in the silicon substrate
101
. Then, a BPSG film
105
is grown on the MOSFET, and then the BPSG film is flattened by the CMP method. Then, a diffusion layer of the MOSFET and a contact hole which reaches the gate electrode are provided for the flattened BPSG film
105
. Polishing-material slurry prepared by dispersing silica colloidal particles in oxidizer solution and the CMP method are used to form the W contact hole plug. A first embedded aluminum circuit in which aluminum is embedded in the first circuit groove formed in the first silicon oxide film
106
is formed on the W contact hole plug. Moreover, a second embedded aluminum circuit is formed by embedding aluminum in a first through hole and a second circuit groove, which are formed in the second silicon oxide film
107
formed above the first embedded aluminum circuit.
The foregoing embedded aluminum circuits are formed in such a manner that aluminum embedded films are formed in the circuit groove and the through holes by a high-temperature sputtering method, and the Al-CMP method with the polishing-material slurry are employed to flatten the surface.
Moreover, a second through hole is formed in an organic film
108
formed on the second siliconoxide film
107
and having a low dielectric constant; a third embedded copper circuit is formed by embedding copper in a third circuit groove; a third through hole is formed; and a fourth embedded copper circuit is formed by embedding copper in a fourth circuit groove. The foregoing embedded copper circuits are formed by embedding copper in the circuit grooves and/or through holes to form copper films by an MOCVD method. Then, the polishing-material slurry is used to perform a CMP polishing operation so as to flatten the surface.
To manufacture the device wafer having the MOSFET, the metal embedding and flattening process using W, Al, Cu, Ti, TiN, WSix, TiSix and the like is frequently employed in a metal CMP method. Also isolation and formation of the flattened device and flattening of the surface of the BPSG film are performed by the oxide-film CMP method.
As shown in
FIGS. 11A
to
11
D, the magnetic head substrate is processed such that a wafer
1
(see
FIG. 11A
) having a substrate
101
on which a permalloy layer
109
is formed. Then, an aluminum insulating layer
110
is furthermore formed. The wafer
1
is polished by the CMP method until the permalloy layer is exposed to the outside (see
FIG. 11D
) by chemimechanically polishing the wafer
1
. As a result, a plurality of the permalloy layers, for example, two to five permalloy layers are sometimes formed.
An automatic (unmanned) polishing means for polishing the wafer has been required from a market. Thus, a variety of CMP automatic polishing apparatuses for automatically detecting an end point of polishing have been suggested. The end point of polishing is detected by any one of the following methods.
(1) The thickness of the wafer which is being polished is measured by a thickness meter to determine the end point in accordance with an amount of polishing (refer to Japanese Patent Laid-Open No. 62-257742, Japanese Patent Laid-Open No. 9-193003, Japanese Patent Laid-Open No. 10-106984 and Japanese Patent Laid-Open No. 10-98016).
(2) A method for determine the end point in accordance with a load electric current, voltage or change in the resistance of the motor of the platen or the chucking mechanism which is performing the polishing operation (refer to Japanese Patent Laid-Open No. 61-188702, Japanese Patent Laid-Open No. 6-252112, Japanese Patent Laid-Open No. 8-99625, Japanese Patent Laid-Open No. 9-70753, Japanese Patent Laid-Open No. 10-44035, Japanese Patent Laid-Open No. 10-128658 and Japanese Patent Laid-Open No. 10-177976).
(3) A method of determining the end point of polishing in accordance with change in the torque of the motor of the platen or the chucking mechanism which is performing the polishing operation (refer to Japanese Patent Laid-Open No. 5-138529, Japanese Patent Laid-Open No. 6-216095, Japanese Patent Laid-Open No. 8-139060, Japanese Patent Laid-Open No. 8-197417, Japanese Patent Laid-Open No. 9-36073, Japanese Patent Laid-Open No. 9-262743 and Japanese Patent Laid-Open No. 10-256209).
(4) A method in which the wafer being polished is irradiated with a laser beam to determine the end point of polishing in accordance with the quantity of reflected light (refer to Japanese Patent Laid-Open No. 57-138575, Japanese Patent Laid-Open No. 61-214970, Japanese Patent Laid-Open No. 4-255218, Japanese Patent Laid-Open No. 5-309559, Japanese Patent Laid-Open No. 7-328916, Japanese Patent Laid-Open No. 8-174411, Japanese Patent Laid-Open No. 9-7985 and Japanese Patent Laid-Open No. 10-160420).
(5) A method in which phosphorus or tracer particles serving as an index is added to the polishing-material slurry to measure the quantity of the index on the
Ide Satoru
Itho Toshihiro
Tanaka Kiyoshi
Lund Jeffrie R.
MacArthur Sylvia R.
Nikon Corporation
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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