Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
1999-05-12
2001-03-20
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S014000
Reexamination Certificate
active
06204075
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to detecting defects of wiring in semiconductor devices. More particularly, the present invention relates to a circuit and a semiconductor wafer used for detecting defects of wiring used for detecting the existence and nonexistence of abnormal conditions in a process for forming conductors or wiring in a manufacturing line of semiconductor devices, and a method for detecting defects of wiring using such a circuit and semiconductor wafer.
BACKGROUND OF THE INVENTION
Defects of wiring or conductors, especially short circuits of wiring or conductors, in a semiconductor device are fatal defects and it is impossible to ship semiconductor devices having such defects as quality products. That is, defects of wiring have a large influence on the yield of semiconductor manufacturing. Therefore, in order to improve the yield, it is extremely important to prevent defects of wiring beforehand.
In order to prevent such defects of wiring beforehand, one or more wafers for detecting defects of wiring are periodically introduced into the manufacturing line of semiconductor devices.
FIGS. 6 and 7
illustrate conventional test patterns formed on a semiconductor wafer for detecting defects of wiring. In particular, such test patterns are formed on a semiconductor wafer in a manufacturing line to be tested and the test patterns formed are inspected, and thereby examination is performed on whether or not formation of wiring is normally attained in this manufacturing line.
Explanation will now be made on the conventional test patterns shown in
FIGS. 6 and 7
.
FIG. 6
is a plan view of the test patterns, and
FIG. 7
is a schematic cross sectional view of the test patterns shown in FIG.
6
. As shown in these drawings, test pads
34
and test wires
36
are formed on an insulation layer or film
32
which covers a semiconductor substrate
30
. As shown in
FIG. 6
, each of the test pads
34
is formed such that each of the test pads
34
is in an electrically floating condition. The test wires
36
are electrically connected to one portion in that a portion of each of the test wires
36
are commonly connected to a diffusion layer
40
provided on the semiconductor substrate
30
, via a contact hole
38
, as shown in FIG.
7
. These test patterns are formed on the whole surface of the wafer for detecting defects of wiring in a manufacturing line to be tested.
Now, explanation will be made of a method for detecting defects of wiring using the above-mentioned wafer for detecting defects of wiring. First, a semiconductor wafer on which no test patterns are formed is introduced into a manufacturing line to be tested, and test patterns shown in
FIGS. 6 and 7
are formed on such semiconductor wafer to fabricate a semiconductor wafer for detecting defects of wirings. Thereafter, an electron beam is radiated and scanned on each of the test pads
34
of the test patterns formed as mentioned above, and the quantity of electric charge of each of the test pads
34
charged up (accumulated) by the electron beam is measured or observed, for example, by using a SEM (scanning electron microscope).
In this case, a particular quantity of accumulated charge, determined by a capacitance value between each of the test pads
34
and the semiconductor substrate
30
, is observed from each of the test pads
34
. However, if there is an abnormal condition with respect to the wiring
36
, such as deviation of location of a wire, and a wire
36
and a test pad
34
contact or electrically short-circuit each other, the test pad
34
contacting the wire
36
is electrically connected to the semiconductor substrate
30
via the wiring
36
. Therefore, the quantity of electric charge accumulated in the test pad
34
becomes very small.
By observing the quantity of electric charge in each of the test pads
34
, it is possible to detect one or more test pads
34
contacting the wiring
36
. If such one or more test pads
34
are found, it is possible to know that defects of wiring tend to occur in locations where such test pads are found.
The test pattern and method of test mentioned above are described in “IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, P.384-389 (1997)”.
However, in the conventional test patterns mentioned above, since the area of each of the test pads
34
is large, the area used for forming the test wirings
36
becomes narrow and, therefore, precision of the test is deteriorated. Also, since the conventional test patterns greatly differ from wiring patterns of actual semiconductor devices, reliability of the test itself is not high.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a circuit and a semiconductor wafer for detecting defects of wiring and a method for detecting defects of wiring, wherein a malfunction of the fabricating process of wiring in a semiconductor manufacturing line can be detected with high precision.
It is another object of the present invention to provide a circuit and a semiconductor wafer for detecting defects of wiring, and a method for detecting defects of wiring, wherein a malfunction of the fabricating process of wiring in a semiconductor manufacturing line can be detected in a condition near to the actual manufacturing condition, thereby realizing high test reliability.
It is another object of the present invention to provide a circuit and a semiconductor wafer for detecting defects of wiring which can be easily fabricated and which have test patterns near wiring patterns of actual semiconductor devices, and to provide a method for detecting defects of wiring using such a circuit and semiconductor wafer, thereby providing easy and reliable detection of defective wiring.
According to an aspect of the present invention, there is provided a circuit for detecting defects of wiring used for detecting a malfunction of the fabrication process of wiring during semiconductor device manufacturing. The circuit comprises an insulating film formed on a semiconductor substrate, a first wiring which is formed on the insulating film formed on the semiconductor substrate and is in an electrically floating condition, and a second wiring which is formed on the insulating film formed on the semiconductor substrate and is disposed adjacent the first wiring and is in an electrically floating condition. In this circuit structure, the capacitance between the second wiring and the semiconductor substrate is made larger than the capacitance between the first wiring and the semiconductor substrate.
According to another aspect of the present invention, there is provided a method for detecting defects of wiring to detect a malfunction of the fabrication process of wiring during semiconductor device manufacturing. The method comprises forming a plurality of circuits for detecting defects of wiring on an insulating film formed on a semiconductor substrate, in a manufacturing line to be tested. The circuit comprises a first wiring which is in an electrically floating condition, and a second wiring which is in an electrically floating condition and which is disposed adjacent the first wiring. The capacitance between the second wiring and the semiconductor substrate is larger than the capacitance between the first wiring and the semiconductor substrate. The method further comprises scanning an electron beam on the surfaces of the first wiring and second wiring, and detecting secondary electrons emitted from the first wiring and the second wiring.
REFERENCES:
patent: 4417203 (1983-11-01), Pfeiffer et al.
patent: 4650333 (1987-03-01), Crabb et al.
patent: 5821761 (1998-10-01), Shida et al.
patent: 6038018 (2000-03-01), Yamazaki et al.
patent: 2-174138 (1990-07-01), None
patent: 4-314032 (1992-11-01), None
patent: 4-310877 (1992-11-01), None
patent: 5-144917 (1993-06-01), None
Bowers Charles
NEC Corporation
Pert Evan
Young & Thompson
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