Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-21
2003-08-05
Nguyen, Minh (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06604229
ABSTRACT:
FIELD OF THE INVENTION
The present invention in general relates to a method of designing wiring for power sources in a semiconductor chip, and a computer-readable recording medium recorded with a program for making a computer execute this method. More particularly, this invention relates to a method of designing wiring for power sources of installing a plurality of functional blocks including logic-decided functional blocks and logic-undecided functional blocks on a semiconductor chip and wiring the power sources of these functional blocks.
BACKGROUND OF THE INVENTION
A logic-undecided functional block means a functional block that has no logic at all or that has only a part of logic decided. A logic-decided functional block means a functional logic that has all the logic decided. In the present specification, power source wiring also includes a ground wiring in addition to the power source wiring for supplying voltages.
Conventionally, in designing a layout of a semiconductor chip, a floor plan and power source wiring have been designed in the following method when there is a hierarchy in logic-decided functional blocks and logic-undecided functional blocks. First, a rough number of logic gates to be used, a gate utilization rate and power consumption for the hierarchy of the logic-decided functional blocks and logic-undecided functional blocks are obtained by calculation. Based on a result of this calculation, a size of a logic-undecided area is determined. Using this size, a size of an LSI chip is estimated. Then, after a list of all logic net has been prepared, functional blocks are actually installed based on a floor plan. Thereafter, wiring is designed, and a resistor network of the power source wiring is analyzed. When there is shortage in the power supply as a result of the analysis, another floor plan is prepared again from the start. Then, a power source designing, installation and wiring are carried out.
According to the conventional layout designing method, has a disadvantage that it requires a long design process as it is necessary to carry out the floor planning, installation and wiring from the start again when there is shortage in the power supply in the first plan. Further, there is a problem in that the size of logic-undecided area becomes large due to the addition of power sources, which results in an increase in chip size. Further, there is a problem that it is not possible to find a surplus position in the initial estimate.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of designing wiring for power sources in a semiconductor chip capable of installing logic-decided functional blocks and logic-undecided functional blocks together on a semiconductor chip when there are logic-undecided functional blocks, and designing an optimum power source wiring for these functional blocks. It is another object of this invention to provide a computer readable recording medium that stores a computer program which when executed realizes the method according to the present invention.
According to one aspect of the present invention, a width of the power source wiring necessary within a logic-undecided functional block is estimated based on the power consumption information of the logic-undecided functional block. It is possible to determine an area of the logic-undecided functional block using this estimate. In the higher layer, the power source wiring is provisionally provided between a logic-decided functional block and the logic-undecided functional block. By analyzing the resistor network of this provisional wiring, it is possible to estimate an optimum width of the power source wiring. Therefore, even when an actual designing of the power source wiring within the logic-undecided functional block of which logic has been decided is carried out once after the designing of the power source wiring in the higher layer has been finished, the actual width of the power source wiring within the logic-undecided functional block becomes equal to or smaller than the width estimated earlier. Further, the actual width of the power source wiring in the higher layer also becomes equal to or smaller than the width estimated earlier.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.
REFERENCES:
patent: 5537328 (1996-07-01), Ito
patent: 5824570 (1998-10-01), Aoki et al.
patent: 10-135339 (1998-05-01), None
Banno Koji
Inui Masuo
Nawa Takanori
Osajima Toru
Suzuki Kenji
Fujitsu Limited
Nguyen Minh
Staas & Halsey , LLP
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