Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-15
2003-01-28
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06513146
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of partitioning specifications and functions required in designing a semiconductor integrated circuit device between hardware implementation and software implementation.
It is conventionally significant to determine, in design of a semiconductor integrated circuit device, which part of specifications and functions required for the system is implemented by software and which part is implemented by hardware. This is because significant characteristics such as the power consumption, the layout area and the throughput are affected depending upon how they are partitioned between software implementation and hardware implementation.
In design of a semiconductor integrated circuit device, a designer appropriately partitions the specifications and functions required for the system between hardware implementation and software implementation in consideration of developing process techniques, circuit techniques and device characteristics. Thus, the partitioning is currently entrusted to the skill of a designer.
Since the scale of a semiconductor integrated circuit device to be designed is enlarging and a large scaled system designated as a system LSI is desired to be constructed, it is difficult to improve the design efficiency merely by relaying upon the skill of a designer.
Accordingly, a technique for automatic partitioning between hardware implementation and software implementation is desired in the design of a semiconductor integrated circuit device. There remain, however, a number of unsolved problems in how the partitioning is automated with stress laid on which characteristic.
SUMMARY OF THE INVENTION
An object of the invention is realizing automatic partitioning between software implementation and hardware implementation by using a processing quantity and power consumption as parameters, generating an interface between hardware and software necessary in the partitioning and providing further means for increasing a processing speed and reducing power consumption.
The first method of designing a semiconductor integrated circuit device of this invention comprises the steps of (a) extracting description parts describing a loop processing part or a function by analyzing a system operation description language describing operations of the semiconductor integrated circuit device to be designed; (b) partitioning each of the description parts extracted from the system operation description language into a H/W implemented description when a processing quantity corresponding to a number of clock cycles of the description part exceeds a threshold value and into a S/W implemented description when the processing quantity is smaller than the threshold value; (c) calculating a sum of the processing quantities of the description parts as a total processing quantity; and (d) determining whether or not the calculated total processing quantity meets a condition.
According to this method, appropriate S/W and H/W partitioning can be automatically conducted with appropriately keeping the total processing quantity of the semiconductor integrated circuit device. In particular, by initially setting not only the condition but also a threshold value of a processing quantity of a description part to be implemented by H/W, it is possible to avoid a problem that a layout area and power consumption are too large due to too many H/W implemented description parts. In this method, simulation may be conducted, but the S/W and H/W partitioning can be carried out by checking the contents of the description parts of the system operation description language through a source code analysis without conducting simulation.
The first method can further comprise a step (e) of converting a description of one of the description parts and returning to the step (c) when the total processing quantity does not meet the condition in step (d), so that the step (e) can be repeatedly conducted until the total processing quantity meets the condition. In this manner, a constraint derived from the threshold value can be gradually eased, so as to design a semiconductor integrated circuit device satisfying the desired condition.
Furthermore, when the total processing quantity does not meet the condition after conducting the step (e) on all of the description parts, a procedure can return to the step (b) after easing the condition. In this manner, a state where the design is impossible because of an unreasonable condition can be avoided.
The threshold value can be given as a number of condition divergences appearing in the description part.
Also, the condition can be a desired range or an upper limit of the total processing quantity.
The first method of designing a semiconductor integrated circuit device can further comprise a step of obtaining total power consumption on the basis of all of the description parts partitioned between the H/W implemented description and the S/W implemented description, and when the total power consumption does not meet a condition, a procedure can return to the step (c) after converting a description of one of the description parts. In this manner, the S/W and H/W partitioning can be conducted also in consideration of power consumption.
The second method of designing a semiconductor integrated circuit device of this invention comprises the steps of (a) obtaining power consumption of each function by analyzing functions included in a system operation description language describing operations of the semiconductor integrated circuit device to be designed; (b) partitioning the function into a H/W implemented function when the power consumption of the function exceeds a threshold value and into a S/W implemented function when the power consumption is smaller than the threshold value; (c) calculating a sum of the power consumption of all of the functions as total power consumption by estimating the power consumption of each function; and (d) determining whether or not the calculated total power consumption meets a condition.
According to this method, the S/W and H/W partitioning for reducing power consumption can be automatically conducted. Accordingly, the efficiency in designing an LSI with small power consumption and the performance of the semiconductor integrated circuit device to be designed can be both improved.
In the second method, at least a use frequency of a general operation instruction in the function can be analyzed in the step (c), and the threshold value can be a value corresponding to an effect to reduce power consumption attained by H/W implementation of the function.
Alternatively, at least an invoke frequency of the function can be analyzed in the step (c), and the threshold value can be a value obtained by partitioning a value corresponding to an effect to reduce power consumption attained by H/W implementation of the function by a smallest processing quantity among processing quantities of the functions.
When the total power consumption does not meet the condition in the step (d), the step (c) can be repeatedly conducted after reducing the threshold value.
Furthermore, probability of increase of an operation speed through H/W implementation can be further analyzed in the step (c), and when throughput attained after increasing the operation speed is larger than throughput attained before increasing the operation speed, the function can be implemented by H/W. In this manner, a semiconductor integrated circuit device with large throughput can be designed in consideration of probability of employment of parallel processing and pipeline processing.
In this method, power optimization can be conducted in the step (c) by at least one of reduction of an operation frequency of each function, use of gated clock, reduction of a supply voltage and bus coding.
Furthermore, when the condition of the step (d) is that a value obtained by multiplying a processing quantity of the function attained through H/W implementation by power consumption of a unit process of a processor is larger than power consumption of the function attained through
Kondo Takahiro
Nakamura Tsuyoshi
Otsuki Hiroki
Sasaki Takayuki
Yonezawa Tomonori
Dinh Paul
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Smith Matthew
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