Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-07
2003-04-15
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06550050
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of and an apparatus for designing a semiconductor integrated circuit device, and particularly to a method of and an apparatus for designing a semiconductor integrated circuit device, which are capable of ensuring operations without delay calculations at an early stage of the development of the semiconductor integrated circuit device.
2. Description of the Related Art
It is necessary that the waveform rounding of a signal inputted to each of circuit cells constituting a semiconductor integrated circuit device is limited to within a predetermined time to assure gate delay times and operating timings for the semiconductor integrated circuit device. Since the waveform rounding is determined according to an input load capacitance of a next-stage circuit cell drivable by an output circuit of each circuit cell, and a wiring load, restrictions on the waveform rounding have heretofore been carried out by methods shown below.
According to a designing method offered in a TLF version 4.1 of Cadence Co., Ltd., for example, the maximum load capacitance drivable by an output circuit of each circuit cell is defined as the maximum drive load capacitance in the form of a LOAD_LIMIT function. When a sum obtained by adding input load capacitances of all next-stage circuit cells connected to the output circuits and capacitive components of all wirings connected to the next-stage circuit cells as one load capacitance exceeds the maximum drive load capacitance, warning is outputted, whereby the gate delay times and the waveform roundings are restricted to ensure the operating timings.
In Japanese Laid-Open Patent Publication No. 2000-20574, a waveform calculator
9
performs circuit simulations, based on an extracted parasitic resistance/parasitic capacitance to provide a connection rule check system dependant on the frequency at which the stability of the operation of a circuit can be confirmed with high accuracy, and a connection rule check method therefor to thereby calculate waveform roundings at output and input terminals of each cell and waveform amplitude values at the input terminals. A waveform comparator
10
compares the calculated waveform rounding values and waveform amplitude values with specified limit values of waveform rounding values and waveform amplitude values stored in a waveform library. According to the result of comparison by the waveform comparator
10
, a circuit configuration change unit
11
changes a circuit configuration and a layout wiring change unit
12
changes layout/wiring.
FIG. 1
shows a circuit cell layout control flow used when wiring delays are determined by calculation in a prior art. Prior to the determination of a circuit cell layout, the extraction of parameters in circuit cells is executed (S
105
). A cell library (D
103
) corresponding to input capacitances, waveform rounding specifications of input signals, output drive capacities, etc. is ensured. Next, the circuit cell layout is temporarily determined (S
104
) based on circuit net information (D
1
) obtained at the stage of the completion of a circuit design for a semiconductor integrated circuit device to thereby obtain wiring information (D
102
) such as a resistance value of each wiring path, wiring load capacitances, etc.
A net to determine a circuit cell layout is selected (S
1
), and a delay from an intended or target circuit cell to a next-stage circuit cell is calculated (S
101
) based on the net information (D
1
), wiring information (D
102
) and cell library (D
103
). It is determined from the result of calculation whether each wiring path (S
106
) satisfies a delay specification of a signal inputted to the next-stage circuit cell (S
102
). If such a condition is not met (S
102
: NO), then the position of the layout of the circuit cell is changed (S
104
) where a change in circuit cell layout is allowed (S
9
: YES). When it is determined that it is necessary to change the circuit cell to one larger in drive capacity (S
9
: NO), the circuit cell is changed (S
103
) and the wiring information (D
102
) is changed. Thereafter, similar processing is repeated (S
13
: YES, S
101
). If the delay specification of the input signal is met (S
102
: YES), then the routine procedure returns to S
106
where similar processing is effected on other wiring paths (S
107
: NO). After the processing has been effected on all the wiring paths, the above processing is repeated with respect to all nets (S
7
: NO). The circuit cell layout is terminated after the completion of the processing on all nets (S
7
: YES). Step (S
101
) for performing the delay calculation and Step (S
102
) for determining whether the result of calculation satisfies the delay specification of the input signal to the next-stage circuit cell, are effected on all the wiring paths (S
16
, S
107
), whereby a part (C
100
) for determining the possibility of driving of a wiring between the circuit cells is configured.
In the designing method offered in the TLF version 4.1 of Cadence Co., Ltd., however, the load capacitance is compared with the maximum drive load capacitance defined using the LOAD_LIMIT function inclusive of a capacitance value obtained by collectively adding load capacitances present on the wiring on a distributed constant basis to thereby determine a delay limit point. Since, however, the value calculated as the load capacitance value of the wiring becomes the sum of capacitance values widely distributed over the wiring on a distributed constant basis, differences in wiring topology, branch position, etc. cannot be reflected on each capacitance value. Waveform roundings, which actually propagate through a wring, differ according to the differences in their topologies as shown in FIG.
2
. It is understood that even when total wiring lengths shown in
FIG. 2
are equal to one another and the respective sums of wiring load capacitances are equal to one another, waveform roundings of next-stage inputs are much different from one another. Thus, the designing method offered in the TLF version 4.1 has a problem in that it cannot recognize the difference between the waveform roundings due to the differences in wiring topology and wiring branch position where the total wiring lengths are equal and the sums of the wiring load capacitances are equal. A problem also arises in that such layout wiring as to hold each waveform rounding within a predetermined limit value cannot be carried out.
In the connection rule check system and connection rule check method therefor according to Japanese Laid-Open Patent Publication No. 2000-20574, the circuit simulations are carried out based on the extracted parasitic resistance/parasitic capacitance and the delay calculations of the waveform roundings and the like are executed. Thereafter, the calculated waveform roundings and the like are compared with the specified limit values such as the waveform rounding values stored in the waveform library. Thus, a problem arises in that while the accurate waveform roundings can be calculated, it is necessary to perform delay calculations based on circuit simulations every wiring path, and enormous time is required for comparisons between the waveform rounding values and the specified limit values.
Further, the two prior arts have a problem in that the waveform roundings cannot reliably be held within the predetermined limit value. Therefore, there is the possibility of re-action of design work such as changes in layout wiring and layout cell, thus causing a problem leading to a bottleneck in the shortening of a period for the development of a semiconductor integrated circuit device.
SUMMARY OF THE INVENTION
The present invention has been made to solve the problems developed in the prior arts. Therefore, the present invention aims to provide a method of and an apparatus for designing a semiconductor integrated circuit device, which are capable of causing each waveform rounding to fall within a predetermined limit value and thereby assuring circuit operations for the s
Fujita Miyako
Hosono Toshikatsu
Wakita Makoto
Yoneda Takashi
Dimyan Magid Y
Fujitsu Limited
Siek Vuthe
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