Method of designing semiconductor integrated circuit and...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

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07409655

ABSTRACT:
A method of designing a semiconductor integrated circuit having a plurality of transistors calculates a leak current corresponding to a sum of a gate leak and a channel leak at each node in the semiconductor integrated circuit, estimates a voltage drop value due to the calculated leak current, determines whether or not the voltage drop value exceeds a threshold value for each node, and inserts a buffer to a node determined that the voltage drop value exceeds the threshold value.

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patent: 2005/0198594 (2005-09-01), Itaka
Koji Nii, et al., “A 90nm Low Power 32K-Byte Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Applications”, 2003 Symposium on VLSI Circuits, Digest of Technical Papers, 2003, pp. 247-250.

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