Method of designing semiconductor integrated circuit and...

Details Method of designing semiconductor integrated circuit and... Method of designing semiconductor integrated circuit and...

2000-06-13

2003-03-25

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06539530

ABSTRACT:

FIELD OF THE INVENTION
The present invention mainly relates to a method for designing a standard-cell type semiconductor integrated circuit and a standard-cell type semiconductor integrated circuit. More particularly, the present invention relates to a placement and routing method to be employed when a logic macro-cell registered in a library is optionally rotated for placement and power source lines are circularly disposed around the logic macro-cell.
A standard cell is one type of ASIC (Application Specific Integrated Circuit) cell. A standard cell is an application specific IC that is manufactured by using logic macro-cells which are registered in a library. Logic macro-cells refer to those ranging from basic blocks, such as NAND gates, NOR gates, inverters, flip-flops, counters, adders, decoders, multiplexers and the like to high performance blocks, such as CPU cores that implement these basic blocks, memory blocks such as RAMs and ROMs and the like. A semiconductor integrated circuit realizes required functions by inputting and outputting signals through the respective logic macro-cells.
A standard cell system enables a design with stress being placed on characteristics of logic macro-cells, unlike a gate array system. Also, due to a high degree of freedom in the layout of logic macro-cells, a higher integration and a smaller chip size can be achieved by placing them with a high level of integration density.
Logic macro-cells used in standard cells include those that occupy relatively large areas. Power source wirings may be circularly placed around such a logic macro-cell (for example, see Japanese Laid-open Patent Application SHO62-145835).
In recent years, semiconductor apparatuses have multiple metal wiring layers ranging from 2 layers to 6 layers. Metal wiring layers are used to provide connections to power source wirings that supply power source potentials VDD and VSS, within logic macro-cells, between logic macro-cells and between terminals of logic macro-cells and the power source wirings.
In general, aluminum layers are used as wiring layers. For example, a two-layer metal wiring includes a first Al wiring layer and a second Al wiring layer. When wiring routs for the first Al wiring layer and the second Al wiring layer are determined by an automatic placing and routing apparatus, priority wiring directions are allocated to the respective first and second Al wiring layers. This will be described below with reference to FIG.
8
.
FIG. 8
shows a routing diagram for a logic macro-cell having circularly placed power source wirings.
FIG. 8
shows, for example, a rectangular logic macro-cell region
400
that is composed of a plurality of basic cells connected with one another. A circular power source wiring layer
401
is formed around the rectangular logic macro-cell region
400
. The circular power source wiring layer
401
includes an inside power source wiring
402
that supplies, for example, a power source potential VSS, and an outside power source wiring
403
that supplies, for example, a power source potential VDD.
Also, power supply wirings
404
-
407
are provided for supplying power from the inside and outside power source wirings
402
and
403
to the logic macro-cell region
400
.
It is noted that the wirings
402
-
407
are formed according to predetermined priority wiring directions. In this example, the wirings in a lateral direction in
FIG. 8
are formed by the first Al layer, and the wirings in a vertical direction in
FIG. 8
are formed by the second Al layer.
Accordingly, the inside metal wiring
402
includes first layer Al wirings
408
and
409
in the lateral direction and second layer Al wirings
410
and
411
in the vertical direction and vias
412
-
415
at four corners thereof for connecting the wirings
408
-
411
to one another.
In a similar manner, the outside metal wiring
403
includes first layer Al wirings
416
and
417
extending in the lateral direction and second layer Al wirings
418
and
419
extending in the vertical direction and vias
420
-
423
at four corners thereof for connecting the wirings
416
-
419
to one another.
The power supply wirings
404
-
407
are formed with the second layer Al wirings, and connected to the first layer Al wirings
408
,
409
,
416
and
417
, respectively, through vias
424
-
427
.
A signal wiring
430
is led from the logic macro-cell region
400
to an outside of the inside and outside power source wirings
402
and
403
. When the wiring
430
is formed, for example, along the lateral direction in
FIG. 8
, the wiring
430
is formed with the first layer Al wiring.
With the structure described above, the power supply wirings
404
-
407
are connected to the inside and outside power source wirings
402
and
403
. In particular, the power supply wirings
406
and
407
are connected to the outside power source wiring
403
without being obstructed by the inside power source wiring
402
.
In the case of the above-described standard cell, when logic macro-cells pre-registered in a library are placed when designing an IC, identical logic macro-cells may be disposed in different orientations in different chips or within one chip (see Japanese Laid-open Patent Application HEI 4-94556). For example, with respect to the logic macro-cell region
400
shown in
FIG. 8
, a logic macro-cell region
500
shown in
FIG. 9
is rotated clockwise through 90 degrees for placement.
A circular power source wiring layer
501
shown in
FIG. 9
also includes an inside power source wiring
502
and an outside power source wiring
503
. Priority wiring directions of wirings
508
-
511
and
516
-
519
that respectively form the inside power source wiring and the outside power source wiring
502
and
503
and power supply wirings
604
-
507
are reversed with respect to those of the wirings
408
-
411
,
416
-
419
and
404
-
407
shown in FIG.
8
.
More specifically, the first layer Al wiring extends in the lateral direction in FIG.
8
and the second layer Al wiring extends in the vertical direction in FIG.
8
. In contrast, the second layer Al wiring extends in the lateral direction in FIG.
9
and the first layer Al wiring extends in the vertical direction in FIG.
9
. In other words, the wirings
504
-
507
shown in
FIG. 9
are also rotated clockwise through 90 degrees with respect to the wirings
404
-
407
shown in FIG.
8
. With this structure, the data for the logic macro-cell region
400
shown in
FIG. 8
can be used for the logic macro-cell region
500
shown in
FIG. 9
as it is. It is noted that the power source wirings
508
-
511
and
516
-
519
are connected in a ring shape by vias
512
-
515
and
520
-
523
.
It is noted that the above-described implementation is an exceptional one, and logic macro-cells other than the logic macro-cell region
500
have first layer and second layer Al wirings that are provided in accordance with the normal priority wiring directions.
However, a signal wiring
530
that is led from the logic macro-cell region
500
to an outside of the inside and outside power source wirings
502
and
503
shown in
FIG. 9
cannot be formed only with the first layer Al wiring, unlike the signal wiring
430
shown in FIG.
8
. If the signal wiring
530
is to be led in the vertical direction of
FIG. 9
only with the first Al wiring, the signal wiring
530
would make a short circuit in a logic macro-cell to which the signal wiring
530
extends with a signal wiring or a power source wiring that is formed therein with a first Al wiring extending in the lateral direction. Alternatively, if the signal wiring
530
extending in the vertical direction is to be made only with the second layer Al wiring in a normal manner, the signal wiring
530
makes a short circuit with the power source second layer Al wirings
511
and
519
.
As a countermeasure, the signal wiring
530
needs to be provided with a region formed with a first layer Al wiring
531
that passes over the power source second layer Al wirings
511
and
519
, as shown in FIG.
9
. Both ends of the region need to

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