Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-05-25
2003-08-05
Pham, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06604234
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to manufacture of semiconductor integrated circuit devices and to formation of a connection conductor pattern of semiconductor integrated circuits having built-in ROMs (Read-Only Memories). For example, this invention relates to a technology for forming a plurality of semiconductor integrated circuit chips storing an inherent code in each built-in ROM on a wafer.
As disclosed in JP-A-8-139208 (laid open on May 31, 1996), for example, semiconductor integrated circuit devices having ROMs each storing therein inherent data are manufactured by serially conducting first the step of forming a common connection conductor pattern and then the step of writing data to be stored into ROM.
SUMMARY OF THE INVENTION
According to the observation acquired by the present inventors, designing/manufacturing of the semiconductor integrated circuit devices described above can be accomplished by a procedure shown in
FIG. 1
of the accompanying drawings.
Referring to
FIG. 1
, a common connection conductor pattern is read out from a common connection conductor pattern file CLFL to generate a common connection conductor pattern
100
A. This pattern
100
A is then stored in a common connection conductor pattern exposure data file LDFL.
On the other hand, a ROM code
1010
is read out from a ROM code file RCFL that stores the ROM code to be stored in the ROM of each chip, and a ROM pattern is generated. The ROM pattern
100
B is stored in a ROM pattern exposure data file RDFL that is separate from the common connection conductor pattern file CLFL storing the common connection conductor patterns of circuits other than the ROM. An electron beam exposure apparatus
200
A exposes first the common conduction conductor patterns of the circuits other than the ROM to generate a mask MSK. The common connection conductor pattern is then formed on a wafer WFR in step
1
by using the mask MSK so formed. The ROM pattern is read out from the ROM pattern exposure data file RDFL and is directly exposed by an electron beam exposure apparatus
200
B an a resist film on the wafer WFR in step
2
to form the ROM pattern. In other words, a different step (different metal layer) from that of the common connection conductor pattern is employed to form the ROM pattern.
The technology described above with reference to
FIG. 1
is directed to semiconductor integrated circuit devices of the type in which a size of chips formed on a single wafer is at least 10 mm square, and the number of kinds of semiconductor integrated circuits (kinds of models) having different ROM patterns, that determine memory data of ROMs, and formed on a single wafer, is at most 50 to 60 kinds. Therefore, the exposure data quantity handled by the electron beam exposure apparatuses for exposing the ROM patterns is not particularly great, and the existing electron beam exposure apparatus can expose the ROM patterns of all the chips on a single wafer or a single mask.
When developing semiconductor integrated circuit devices having different patterns of ROMs that have chip sizes of not greater than 1 mm square, for example, and are to be built in the semiconductor integrated circuit devices, respectively, the present inventors have studied feasibility of technologies for designing and manufacturing mutually separately common connection conductor patterns of circuits other than ROMs and ROM patterns, and have acquired the following observation. In the case of semiconductor integrated circuit devices having a chip size of not greater than 1 mm square, for example, the technology for designing and manufacturing individually the common connection conductor pattern other than the ROM and the ROM patterns needs an exposure data file number of as great as 50,000 to 600,000 because 50,000 to 600,000 chips need to be formed on a single wafer. Thus, the exposure data quantity becomes as great as 500 GB (giga byte) to 600 GB.
In this case, a large-scale magnetic disk apparatus has to be connected to the electron beam exposure apparatus to store the exposure data. Further, a transfer time to transfer the exposure data from the magnetic disk apparatus to a memory device for exposure gets elongated to one or more days, for example, when exposure is performed. The present inventors have thus clarified that the existing electron beam exposure apparatus cannot practically form the ROM patterns about all the chips on a single wafer on the wafer or a single mask.
In view of the problems described above, the present invention aims at providing a technology that can eliminate a dedicated step for forming a pattern (ROM pattern) determining memory data of a built-in ROM on a resist film, can simplify a manufacturing process and can reduce a manufacturing cost.
It is another object of the present invention to provide a technology that can reduce the number of exposure pattern data files handled, and can expose ROM patterns of all the chips on a single wafer by using en existing electron beam exposure apparatus.
These and other objects and novel features of the present invention will become more apparent from the following description of the specification taken in connection with the accompanying drawings.
According to one aspect of the present invention, there is provided a method of designing/manufacturing a plurality of semiconductor integrated circuits having built-in ROMS each storing different data on a single wafer, wherein a pattern for determining memory data of a built-in ROM (hereinafter called “ROM pattern”) is simultaneously formed by combining the pattern with a common pattern, that is common to a plurality of semiconductor circuits other than this pattern, on a resist film or a photosensitive film. In consequence, a dedicated step of forming the ROM pattern on the resist film or the photosensitive film becomes unnecessary and the manufacturing process can be simplified.
According to another aspect of the present invention, there is provided a method of designing/manufacturing a plurality of semiconductor integrated circuits having built-in ROMS each storing different data on a single wafer, comprising the steps of forming a ROM pattern for determining memory data of the built-in ROM by using the uppermost metal layer of a plurality of metal layers; combining the ROM pattern with at least part of a common pattern common to the plurality of semiconductor circuits other than the pattern into a combined connection conductor pattern; performing pattern exposure of the combined connection conductor pattern to a resist film applied to a surface of the wafer by using an electron beam exposure apparatus to simultaneously form the ROM pattern and a part of the common connection conductor pattern; and forming patterns other than the combined connection conductor pattern by using a mask. To form a plurality of semiconductor integrated circuit devices each having different data to be stored in its built-in ROM on a single wafer, a mask must be prepared for each wafer if the mask is used for forming a ROM pattern, with the result that the manufacturing cost becomes remarkably high. When pattern exposure by an electron beam apparatus is employed to form the ROM pattern, however, the cost can be drastically reduced. Moreover, because a dedicated step of forming the ROM pattern on a resist film becomes unnecessary, the manufacturing process can be simplified. Because the ROM pattern is formed from the uppermost metal layer, TAT (Turn-Around Time) can be shortened when any change must be made to the ROM pattern.
According to still another aspect of the present invention, there is provided an inspection method of a semiconductor integrated circuit device comprising a built-in ROM for storing different data, a transmitting circuit for non-contactually transmitting data to an external device and an antenna for transmission, whereby the transmitting circuit transmits memory data of the built-in ROM to outside, the inspection method comprising the steps of receiving memory data of the built-in ROM transmitted from the transmitting circu
Suzuki Toshio
Usami Mitsuo
LandOfFree
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