Method of designing layout of semiconductor integrated...

Details Method of designing layout of semiconductor integrated... Method of designing layout of semiconductor integrated...

2006-03-16

2008-11-18

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07454734

ABSTRACT:
A method of designing a layout of functional blocks and on-chip capacitors in a semiconductor integrated circuit, includes the steps of, in sequence, (a) placing a functional block, (b) placing an on-chip capacitor in an area which remains vacant after the step (a) has been carried out, (c) overlapping a portion of the functional block having been placed in the step (a) and a portion of the on-chip capacitor having been placed in the step (b) each other, if possible, and (d) placing an on-chip capacitor in a vacant area caused by carrying out the step (c).

REFERENCES:
patent: 6305002 (2001-10-01), Uchida
patent: 6480992 (2002-11-01), Runyon
patent: 6546538 (2003-04-01), Rubdi et al.
patent: 7-106521 (1995-04-01), None
patent: 10-144797 (1998-05-01), None
patent: 11-168177 (1999-06-01), None
patent: 2001-203272 (2001-07-01), None

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