Method of designing layout of semiconductor device

Details Method of designing layout of semiconductor device Method of designing layout of semiconductor device

2006-02-07

2006-02-07

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06996794

ABSTRACT:
This invention provides a method and system for designing the layout of a semiconductor device that appropriately arranges various types of auxiliary cells in vacant areas. The method of the present invention is devised for laying out a plurality of auxiliary cells between logic cells in a semiconductor device. The present invention further provides an apparatus comprising a processor configured to carry out the inventive method. The apparatus of the present invention may include a cell library in which the auxiliary cells are registered and dummy cells are utilized. The present invention additionally provides a computer readable storage medium, containing a program code instructed to perform the method of the present invention.

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