Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-12-06
2003-12-30
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06671858
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a technology for laying out the arrangement of and wiring between a high-order hierarchical functional block on one hand and a plurality of low-order hierarchical functional blocks constituting the high-order hierarchical functional block on the other.
BACKGROUND OF THE INVENTION
In case of a semiconductor integrated-circuit device designed in accordance with a cell base, desired functions have been realized so far as follows. Cells which are already-designed basic circuits including logic circuits such as the AND circuits, OR circuits, flip-flops, or memories are arranged in a predetermined area in a chip and wiring signal connections between each of these logic circuits. Because of recent improvement of the semiconductor fabrication art, it has become possible to mount more functions on one chip whereby the number of gates mounted on one chip has increased drastically. Consequently, the significance of a layout process for arrangement of and wiring between cells has risen.
A hierarchical-layout technique has been frequently used in deciding a layout of a large-scale semiconductor integrated-circuit device. In the hierarchical-layout technique, layout is performed for each one of a plurality of functional blocks, and layout of the semiconductor integrated-circuit device is performed by considering the layouts of the functional blocks.
FIG. 5
concretely explains how a hierarchical-layout design is obtained using the conventional hierarchical-layout technique. As shown in
FIG. 5
, a semiconductor integrated-circuit device
100
is provided with a core area
110
in which a group of integrated circuits is located, and a buffer area
120
in which a group of peripheral circuits is located.
A high-order hierarchical functional block
111
is located in the core area
110
and a plurality of low-order hierarchical functional blocks
112
,
113
,
114
, and
115
are arranged in the formation area of the high-order hierarchical functional block
111
at both sides of an inter-block wiring area
116
.
Signal connection terminals
117
are provided for the circumference of each of the low-order hierarchical functional blocks
112
to
115
and connected by signal connection wirings
118
laid in the inter-block wiring area
116
.
In case of conventional hierarchical-layout design, the signal connection terminals
117
for the low-order hierarchical functional blocks
112
to
115
are decided as a high-order hierarchical-layout design and then, the low-order hierarchical functional blocks
112
to
115
are arranged in the core area
110
having a predetermined size by securing the inter-block wiring area
116
necessary and sufficient to connect the blocks
112
to
115
each other. Moreover, internal wiring of each of the low-order hierarchical functional blocks
112
to
115
is executed. Subsequently, the signal connection terminals
117
are connected to each other by signal connection wirings
118
as a high-order hierarchical-layout design.
In the case of conventional hierarchical-layout design, however, signal connection terminals of low-order hierarchical functional blocks are decided for high-order hierarchical-layout design and then cell arrangement and wiring of the low-order hierarchical functional blocks are performed. Therefore, positions of the signal connection terminals restrict the layout of cell arrangement and wiring and moreover influence the high-order hierarchical-layout design. As a result, a problem occurs that layout design requires lots of time and labor.
Moreover, an inter-block wiring area is necessary in a core area in order to connect low-order hierarchical functional blocks to each other for high-order hierarchical-layout design. Therefore, a problem also occurs that the integration degree of a semiconductor integrated-circuit device is lowered.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a method of designing a wiring layout of low-order hierarchical functional blocks without setting an inter-block wiring area between the low-order hierarchical functional blocks and thereby designing high-order hierarchical-layout design. It is another object of this invention to provide a computer program that contains instructions which when executed on a computer realizes the method according to the present invention on the computer.
The method of designing a hierarchical-layout of a semiconductor integrated-circuit device according to one aspect of this invention comprises the steps of: deciding an arrangement area where a high-order hierarchical functional block is to be arranged in a core area, the core area being an area in which a group of integrated circuits is formed; deciding arrangement areas where a plurality of low-order hierarchical functional blocks are to be arranged in the arrangement area of the high-order hierarchical functional block in such a manner that the distance between the low-order hierarchical functional blocks is narrow; arranging cells constituting the low-order hierarchical functional blocks in each of the low-order hierarchical functional blocks; setting signal connection terminals for connecting input/output terminals of the arranged cells to the corresponding low-order functional block; connecting the cells constituting the low-order hierarchical function blocks each other by a first wiring layer including a first via in each of the arrangement areas of the low-order hierarchical functional blocks; connecting the low-order hierarchical functional blocks each other by connecting a second wiring layer including a second via different from the first wiring layer including the first via to input/output terminals of the cells to which the signal connection terminals are set via the high-order hierarchical functional block; and connecting the high-order hierarchical functional block with the low-order hierarchical functional blocks by the second wiring layer including the second via which connects the low-order hierarchical functional blocks each other.
According to the above aspect of the present invention, the formation area of a high-order hierarchical functional block is decided in a core area in which a group of integrated circuits is formed and arrangement areas of a plurality of low-order hierarchical functional blocks are decided in the decided formation area of the high-order hierarchical functional block by decreasing intervals between the low-order hierarchical functional blocks. Then, cells constituting the low-order hierarchical functional blocks are arranged in the arrangement areas of the low-order hierarchical functional blocks. In this case, signal connection terminals for connecting low-order hierarchical functional blocks to each other are set to input/output terminals of the arranged cells. That is, the signal connection terminals of the low-order hierarchical functional blocks are set not to the circumference of the low-order hierarchical functional blocks but to low-order hierarchical functional block areas. Then, the cells constituting the low-order hierarchical functional blocks are connected to each other by a first wiring layer including a first via in the arrangement areas of the low-order hierarchical functional blocks. Moreover, the low-order hierarchical functional blocks are connected to each other by a second wiring layer including a second via through the high-order hierarchical functional block and the high-order hierarchical functional block is connected with the low-order hierarchical functional blocks by the second wiring layer including the second via.
The method of designing a hierarchical-layout of a semiconductor integrated-circuit device according to another aspect of this invention comprises the steps of: reconstituting a net list of a semiconductor integrated circuit device to be fabricated into a high-order hierarchical functional block and a plurality of low-order hierarchical functional blocks; deciding hierarchical-layout areas of the reconstituted low-order hierarchical functional blocks with no gap in the
Lin Sun James
Mitsubishi Denki & Kabushiki Kaisha
Smith Matthew
LandOfFree
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