Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-01
2003-03-25
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06539531
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a process of designing, simulating, fabricating, testing and interconnecting integrated circuits (ICs), and in particular to a method for fully integrating the interconnect systems that are to connect ICs to external circuits into all stages of that process.
2. Description of Related Art
Integrated Circuit Process Flow
FIG. 1
illustrates a typical prior art process of designing, fabricating, testing, and connecting an integrated circuit (IC). A design engineer initially develops a design specification (step
400
) abstractly describing the functionality and overall architecture of the IC and then develops a high-level hardware description language (HDL) model of the IC describing how data flows between clocked registers and how the design processes that data (step
402
). The design engineer also programs a circuit simulator (step
404
) to simulate circuit behavior based on the HDL circuit model and may iteratively adjust and simulate the HDL model until verifying that the circuit logic is correct. Since the HDL model is a relatively high level behavioral model of the circuit, simulation can verify circuit logic at step
404
but cannot verify circuit timing because it does not take into account various constraints of the particular semiconductor technology that will implement the IC.
Thereafter, the design engineer usually employs computer-aided logic synthesis tools (step
406
) to convert the high-level HDL circuit model into a lower-level, technology-specific, behavioral model of the circuit such as a netlist. A netlist model typically describes the behavior of circuit components based on models provided by a cell library
410
. Each cell of cell library
410
includes both netlist-level behavioral models and structural models (mask layouts) for each circuit component that may be incorporated into an IC. Cell library
410
may include cells describing low level circuit components such as individual resistors and transistors as well as higher level standard circuit components such as logic gates, memories and central processing units.
During the iterative, synthesis process the design engineer uses a simulator and other tools to verify circuit operation based on the netlist model (step
412
) and may iteratively adjust the HDL model to produce a netlist model that satisfies various constraints on circuit operation defined in the specification and incorporated into the HDL model. Since the netlist model is more closely related to the eventual physical realization of the IC than the HDL model, simulation and special timing verification tools can verify both circuit logic and timing constraints. However, timing constraints verification at this stage of the design may not be entirely accurate since the netlist model does not specify the actual physical positions on an IC chip of the cells that will form the circuit or the actual lengths and impedance characteristics of signal paths between those cells.
Having verified the logic and timing of the netlist circuit model, the design engineer employs additional computer-aided design tools to establish a floorplan (step
414
) fixing locations of the IC's input/output (I/O) terminals and fixing the positions of various large, high level circuit modules included in cell library
410
that are to be placed in particular areas of the IC substrate. Placement and routing tools establish the detailed layout of the various layers of IC, determining where each cell of the IC is to be placed and how the conductors interconnecting those cells are to be routed (step
418
). In addition to a behavioral model of a circuit component, each component cell of cell library
410
also includes a structural model (mask layout) of the circuit component that can be incorporated into the IC layout. The CAD tools performing the floorplanning, placement and routing functions iteratively vary the IC design, subjecting each variation to simulation and verification (step
422
) to determine how well it satisfies the various timing and logic constraints imposed by the specification. Timing verification at this point is more accurate than the timing verification carried out on netlist at step
412
because it takes into account the actual physical layout of the cells and their interconnections.
The output of the placement and placement and routing process
418
is a structural model of the IC in the form of a set of masks telling an IC manufacturer how to fabricate the various layers of the IC. When an IC fabricated on a semiconductor wafer includes a “repairable” embedded memory, a memory test is usually performed (step
428
) while the IC is still in the form of a die on the wafer. “Repairable” memories typically have one or more “spare” rows or columns of memory cells that can replace a row or column containing one or more defective cells. The results of the memory test are subjected to “redundancy analysis” (step
430
) to determine how to best allocate spare rows and/or columns to replace the rows and/or columns containing defective cells. The memory is then repaired (step
432
) using lasers or other means to appropriately alter signal path routing within the IC so that spare rows and/or columns of cells are substituted for rows and columns having defective cells.
After repairing the memory (step
432
), or immediately after fabrication (step
424
) when the IC has no repairable memory, the wafer is “diced” to separate the individual die (step
434
) and packaged (step
436
). The packaged IC may the be subjected to a “burn-in” process (step
438
) wherein it is heated in an oven to place it under the kind of heat stress they it may encounter in its working environment. Thereafter the packaged IC is subjected to logic and parametric testing (step
440
). The packaged IC is later mounted on a circuit board in its intended operating environment (step
442
). The IC testing step
440
can be carried out before the dicing step
434
while the IC is still in the form of a die on the wafer.
Interconnect Systems
As a part of the IC design process, IC designers must concern themselves with the structures that connect nodes of an IC to external circuits. In a typical packaged IC, each circuit node that is to communicate with external circuits is linked to a bond pad on the surface of the IC chip. A bond wire connects the bond pad to a conductive leg extending from the package surrounding the IC chip. When the IC is mounted on a printed circuit board (PCB) the package leg is usually soldered to a PCB trace on the surface of the PCB. When bond pads of one or more other ICs mounted on the PCB are linked to the PCB trace, the bond pads, bond wires, package legs, and the PCB trace form an interconnect system for conveying signals between nodes of two or more ICs. Other interconnect systems are also used. For example, in “solder ball” IC packages the bond wires link the IC pads to balls of solder on the underside of the package that bond to PCB traces when the IC is installed on a PCB.
Spring contact interconnects are becoming popular replacements for bond wire and solder ball interconnect technologies in many applications because they eliminate the need for IC packaging and because they provide a number of other advantages.
FIGS. 2 and 3
are partial sectional elevation views of an IC
10
and an IC
20
employing small wire-spring contacts
16
. The circuits implemented by IC
10
are implemented on a silicon wafer substrate
12
. A separate bond pad
14
is formed at the surface of substrate
12
for each of the IC's I/O signals. In the IC
10
of
FIG. 2
, a conductive wire-spring contact
16
is attached to each bond pad
14
. Each wire-spring contact
16
is suitably formed, for example, by a gold wire welded to the bond pad
14
and coated with a resilient alloy. The unpackaged IC
10
can be installed directly on a printed circuit board (PCB)
17
with the tip
18
of each wire-spring contact
16
contacting a trace
19
on the surface of PCB
17
.
In IC
Long John M.
Miller Charles A.
Bedell Daniel J.
Do Thuan
FormFactor Inc.
Smith Matthew
Smith-Hill & Bedell
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