Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-16
2003-06-24
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06584604
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of designing a DRAM macro-cell. In particular, the present invention relates to a method of designing a DRAM macro-cell suitable for using a CAD (Computer-Aided Design) system for processing arrangement and wiring of a leaf cell that is a functional unit.
Conventionally, in generally designing a compiled macro-cell such as an SRAM or a ROM for inclusion in an ASIC (Application Specific Integrated Circuit), a leaf cell is selected so as to fit required parameter settings such as the number of words or the number of bits, and the selected leaf cell is concatenatedly disposed based on an arrangement template and laid out. An example of the arrangement template is illustrated in
FIG. 7
of Japanese Patent Application Laid-Open No. 6-89937.
For connection between the leaf cells, there is employed a method of a CAD system providing automatic wiring or a method of adjacently disposing leaf cells where wires have already been formed. In addition, in Japanese Patent Application Laid-Open No. 6-89937, there is disclosed a method in which, presuming that automatic wiring will be provided by a CAD system, wiring channels in the leaf cell are provided in advance. Thus, wiring between the leaf cells is restricted in advance, which improves the efficiency (processing speed) of automatic wiring by the CAD system and improves the quality of layout data that is produced.
In the meantime, DRAM macro-cells have a plurality of types of address signals. Thus, even if macro-cells have the same number of words and number of bits a plurality of configurations are produced depending on addressing methods. There is a problem in that applying a general method of designing compiled macro-cells such as SRAMs and ROMs to a compiled DRAM macro-cell causes an increase in types of arrangement templates, an increase in number of leaf cells and an increase in scale of a circuit, which lead to extended development times and an increase in man-hours of operation and management.
SUMMARY OF THE INVENTION
The present invention has been proposed in order to solve the aforementioned problem. It is an object of the present invention to provide a method of designing a DRAM macro-cell, the method being capable of efficiently designing a layout of a macro-cell without increasing a number of arrangement templates.
According to one aspect of the present invention, there is provided a DRAM macro-cell designing method including the steps of: an arrangement template generating step of generating a plurality of arrangement templates stratified in high order and low order so that leaf cells of their same type are mainly continuous among from plural types of leaf cells that configure macro-cells; and a leaf cell disposing step of employing a low-order arrangement template, thereby disposing a predetermined leaf cell and producing a new leaf-cell, and disposing at least the new leaf cell at a high-order template, thereby designing the layout of a macro-cell.
Leaf cells are single layout units at each level of a hierarchy when a layout is provided by a CAD system. DRAM macro-cell parameters include the number of column addresses, the number of bits, the number of banks, and the number of addresses per bank. For macro-cells, plural types of leaf cells are disposed in a predetermined arrangement according to these parameters. At these arrangement templates, leaf cells of the same type are mainly disposed concatenatedly in order to efficiently perform arrangement. Here, the high-order arrangement template is a template provided at a higher level than the low-order arrangement template, irrespective of whether or not an arrangement template is present at an even higher level. Similarly, the low-order arrangement plate is a template provided at a lower level than the high-order arrangement template, irrespective of whether or not an arrangement template is present at an even lower level. At the high-order arrangement template, as well as a leaf cell newly produced by the low-order arrangement template, there may be disposed other leaf cells. In this manner, leaf cells are disposed by employing the stratified arrangement templates, whereby a design corresponding to a DRAM macro-cell configuration can be made speedily and efficiently.
In addition, in the leaf cell disposing step, the low-order arrangement template is employed, leaf cells are thereby disposed in a given direction, and a new leaf cell is produced. Then, the new leaf cell is rotated so as to correspond to the arrangement direction of the high-order arrangement templates. Thus, rotated leaf cells may be disposed in the certain direction by employing the high-order arrangement template. In this manner, leaf cells are always disposed in the given direction, and the design can be made more efficiently.
In addition, in the arrangement template producing step, an arrangement template for disposing a leaf cell which is a wiring channel is generated as the low-order arrangement template. In the leaf cell disposing step, the low-order arrangement template is employed to dispose a predetermined leaf cell and produce a new leaf cell is, and the new leaf cell is disposed by the high-order arrangement template, whereby wiring between leaf cells disposed at the high-order arrangement template may be provided.
Further, in the arrangement template producing step, there may be formed as the high-order and low-order arrangement templates, arrangement templates for disposing predetermined leaf cells and a connection wiring leaf cell for making connection between the predetermined leaf cells in a superimposed manner. As a result, wiring among all the leaf cells can be completed, and wiring connections between the leaf cells can be eliminated.
According to the present invention, there is generated a plurality of arrangement templates mainly stratified such that leaf cells of the same type are concatenated. A low-order arrangement template is employed, whereby predetermined leaf cells are disposed, and a new leaf cell is produced. And at least one new leaf cell is disposed at the high-order arrangement template, whereby the number of arrangement templates is reduced to a minimum, and a design process can be performed efficiently.
REFERENCES:
patent: 5883814 (1999-03-01), Luk et al.
patent: 5943285 (1999-08-01), Kohno
patent: 6002633 (1999-12-01), Oppold et al.
patent: 06-089937 (1994-03-01), None
patent: 09-167170 (1997-06-01), None
Tomoaki Yabe et al., “A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized Using a Memory Generator,” IEEE Journal of Solid-State Circuits, vol. 33, No. 11, Nov. 1998, pp. 1752-1757.
Lin Sun James
Oki Electric Industry Co. Ltd.
Smith Matthew
Volentine & Francos, PLLC
LandOfFree
Method of designing DRAM macro-cell and arrangement template... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of designing DRAM macro-cell and arrangement template..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of designing DRAM macro-cell and arrangement template... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3116010