Method of designing clock wiring

Details Method of designing clock wiring Method of designing clock wiring

2001-09-26

2003-08-19

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06609241

ABSTRACT:

Priority is claimed from Japanese Patent Application No. 2000-292578 filed Sep. 26, 2000, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to relates to a method of designing a clock wiring, and more particularly, but not limited to, a method of designing a clock wiring, where a layout design makes a function block hierarchical. The present application is based on Japanese Patent Application No. 292578/2000, which is incorporated herein by reference.
2. Description of the Related Art
With the advance of semiconductor technology in recent years, an LSI (large-scaled semiconductor integrated circuit) is becoming increasingly high in speed, high in integration, and high in scale. In particular, in a logic circuit, an LSI chip is designed by a so-called deep sub micron design rule of 0.35 &mgr;m or less. There are many high integrated chips using clock frequencies in a range from several hundreds MHz to several GHz.
In the high-speed LSI of this type, it is important to reduce a difference in a clock delay time between functional circuits which causes malfunction, that is, a clock skew.
Generally, as a method of designing a clock transmission wiring (hereinafter referred to as “clock wiring” or “clock wiring method”), a method has been employed that includes conducting a clock tree synthesis from an output terminal of a clock generating circuit to a cell group, which is a functional block to which a clock is supplied. However, an increase in the scale of LSI devices in recent years results in an increase in the number of processes for conducting a layout design and a processing period thereof, so that the conventional design method includes a huge number of processes and a long processing time for designing a single layout.
As is well known, the LSI design process is roughly divided into a functional design for designing the operation to be realized by a functional block having functional parts, a logic design for converting the functional block into a logic circuit, and a layout design for converting the logic circuit into a mask pattern.
When the layout design of the LSI chip takes a wiring delay time into consideration, there is widely employed a layout design method which is a so-called top down system, in which the functional block is made hierarchical.
The functional block is conventionally separated into two hierarchies, a superior hierarchy (hereinafter referred to as “top level”) and an inferior hierarchy (hereinafter referred to as “macro”). A hierarchy design process for obtaining the layouts within each of the top level and the macro, individually, is first used to obtain the layout of the top level.
In order to develop the LSI at a low cost and in a short period of time, it is necessary to reduce the clock skew in the case of conducting the layout design method of the top down system.
Referring to
FIGS. 1A
to
1
C, showing a first conventional method of designing a clock wiring disclosed in Japanese Patent Application Laid-open No. Hei 4-148376, the functional block, to which the clock wiring is applied, includes an output block
1
of a clock net and two macros
2
,
3
, where top level wirings are clock wirings from the output block
1
of the clock net to two macros
2
and
3
. Initially, straight lines
7
and
8
, connecting an output terminal (hereinafter referred to as “clock output terminal”)
11
disposed in the output block
1
of a clock net to the respective centers
25
and
35
of macros
2
and
3
, are drawn to obtain cross points
201
and
301
of the straight lines
7
,
8
and to obtain the respective peripheral edges of the macros
2
and
3
.
Then, as shown in
FIG. 1B
, the cross points
201
and
302
on the peripheral edges of the macros
2
and
3
are obtained on the basis of the longest distance between the clock output terminal
11
and the crosses on the peripheral edges of the macros
2
and
3
. Finally, the arranging process and the wiring process within the macro are conducted with the cross points
201
and
302
being used as the respective outer (clock) terminal positions of the macros
2
and
3
, as shown in FIG.
1
C. Through the above processes, the wirings between the clock output terminal
11
and the respective clock terminals (cross points)
201
and
302
of the macros
2
and
3
become equal in length to each other. When cells are arranged within the respective macros
2
and
3
, the cells
203
and
303
connected to the clock terminals
201
and
302
(hereinafter referred to as “clock terminal connection cells”) are disposed in the vicinity of the clock terminals
201
and
302
, to thereby make the respective distances from the clock output terminal
11
to the clock terminal connection cells
203
and
303
, of the respective internal clock terminals
201
and
302
, equal to each other, thereby eliminating the clock skew.
However, in the first conventional clock wiring designing method, because no input/output separation buffer is added in the vicinity of the clock terminal, and because a delay model of the macro per se is not produced, the delay calculation of the top level, which is necessary for the layout design of the top down system, cannot be conducted with a high precision. The delay calculation of the top level means a delay calculation between the clock output terminal
11
and the respective clock terminal
201
and
302
.
Namely, in the case where the clock wirings of the top level are made equal in length to each other, delay values from the clock output terminal
11
to the respective clock terminals
201
and
302
are different from each other due to a difference in the capacitance between the adjacent wirings caused by a difference of the wirings adjacent to the clock wiring, etc. As a result, even if the clock terminal connection cells
203
and
303
are arranged in the vicinity of the terminals
201
and
302
when the arrangement within the macro is conducted, the respective clock delays, of the clock output terminal
11
and a plurality of clock terminal connection cells
203
and
303
within the macro, are not equal to each other, and the clock skew may be large.
Also, in the case of conducting the delay calculation of the top level, because the functional block (cell) within the macro is not yet arranged, the delay calculation of the top level, which takes into consideration the accurate load after the arrangement within the macro is wired, cannot be conducted.
The flowchart of
FIG. 2
illustrates a second conventional method of designing the clock wiring. A macro arrangement is first conducted (Step P
1
), and the terminal position of the top level is determined (Step P
2
). Then, the CTS (clock tree synthesis) of the top level is conducted, so that the clock skewings between the clock output terminal and the respective clock terminals of the macros coincide with each other (Step P
3
), the arrangement of the top level is implemented (Step P
4
), and the information on the resistors R and the capacitors C of the respective wirings (hereinafter referred to as “RC information”) F
101
is extracted.
After Step P
2
, the arrangements within the respective macros are conducted (Step P
11
), the CTS within the macros is conducted so that the respective macro delays become equal to each other (Step P
12
), the wiring within the macros is implemented (Step P
13
), and an information of a resistance and a capacitance (hereinafter a RC information) F
102
of the respective wirings within the macro is extracted.
The static timing, between the clock output terminal and the clock terminal connection cell within the macro, is determined on the basis of the RC information F
101
and F
102
(Step P
5
), and it is confirmed whether the clock skew is within a given standard value or not (Step P
6
).
If the confirmation result in step P
6
is not acceptable, the delay is adjusted by changing the drive capability of a buffer added to the CTS and adding the buffer or the like (Step P
6
), and Steps P

Affiliated with

Also associated with

Rating

Method of designing clock wiring does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of designing clock wiring, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of designing clock wiring will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3112993