Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2001-02-16
2003-09-30
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S048000, C257S750000, C257S752000, C257S758000, C257S762000, C257S765000, C257S774000, C438S631000, C438S598000, C438S599000, C438S633000, C438S692000, C438S926000, C438S017000
Reexamination Certificate
active
06627926
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor device testing; more specifically, it relates to a structure for visual and electrical test (probing/diagnostics) of semiconductor devices using fill shape patterns incorporated into wiring levels and methods for forming these structures.
BACKGROUND OF THE INVENTION
Advanced semiconductor devices increasingly require more complex wiring schemes to wire together individual elements into circuits. These schemes rely on multilevel structures formed from wiring levels containing conductive wires and interconnect levels containing conductive vias that connect conductive wires on two different wiring levels together.
Fabrication of such multilevel structures often requires the use of a fabrication technique called chemical-mechanical-polishing (CMP) of the wiring levels and the interconnect levels. However CMP can cause variations in the flatness of the top surface of semiconductor devices severe enough to effect the quality of the photolithographic process steps used to define the patterns of wires and vias in the wiring and interconnect levels. Variations in flatness occur most frequently on the wiring levels and are caused by differences in conductive wire densities from region to region on the surface semiconductor level being then fabricated. This creates differences in polish rate so more or less material is removed from one region than another. In an attempt to solve this problem, methods have been developed that distribute fill shapes, formed at the same time and of the same material as the conductive wires, in such a manner as to attempt to keep the density of conductive material and therefore the polishing rate, the same in all regions. Fill shapes are isolated from the conductive wires and do not carry electrical signals or power. Fill shapes are added to the design data during the design process.
FIG. 1
is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating the placement of fill shapes as presently practiced. Semiconductor device
1
is comprised of substrate
10
and via levels
20
,
40
,
60
,
80
,
100
, and
120
alternating with wiring levels
30
,
50
,
70
,
90
,
110
, and
130
. Passivation level
140
seals the device. Wiring levels
50
,
70
,
90
,
110
, and
130
, in addition to having conductive wires also have fill shapes. Fill shapes are designated by the letter “F” in order to more easily distinguish them for the reader. Fill shapes are conductive as well. Conductive level
50
has conductive wire
50
A and fill shapes
52
A through
52
H. Conductive level
70
has conductive wires
70
A through
70
C and fill shapes
72
A and
72
B. Conductive level
90
has conductive wire
90
A and
90
B and fill shapes
92
A through
92
F. Conductive level
110
has conductive wire
110
A and
110
B and fill shapes
112
A through
112
C. Conductive level
130
has conductive wires
130
A and
130
B and fill shapes
132
A through
132
D. Via level
20
has vias
20
A through
20
C connecting conductive wire
30
A with substrate
10
and vias
20
D and
20
E connecting conductive wire
30
B with substrate
10
. Via level
40
has via
40
A connecting conductive wire
30
B with conductive wire
50
A. Via level
60
has via
60
A connecting conductive wire
50
A with conductive wire
70
C. Via level
80
has via
80
A connecting conductive wire
70
A with conductive wire
90
A. Via level
100
has via
100
A connecting conductive wire
90
A with conductive wire
110
A and via
100
B connecting conductive wire
90
B with conductive wire
110
B. Via level
120
has via
120
A connecting conductive wire
110
A with conductive wire
130
A and via
120
B connecting conductive wire
110
B with conductive wire
130
B. All the conductive wires, vias, and fill shapes are held in a matrix of insulator
15
which may be the same insulating material or a different insulating material level to level.
In general insulators are optically transparent or semitransparent while conductors are not in the thickness' used in semiconductor devices. As may be readily seen from
FIG. 1
, the placement of fill shapes of each of the wiring levels has been done independent of any other level so that when doing a visual inspection fill shapes on higher levels can block line of sight views to the lower wiring and interconnect levels of the device, limiting the usefulness of visual inspection for cause of fail or reliability assessment. For example, in
FIG. 1
, only conductive wires
130
A,
130
B and
110
A are directly visible, fill shapes
112
A,
112
B,
112
C, and
92
F blocking the line of sight from the top surface.
Additionally, should electrical probing of lower levels be desired, the fill shapes block direct access to the lower levels either forcing removal of higher levels and subsequent loss of some or all of the device functionality or the milling of an access hole through the dielectric
15
and fill shapes in the path with the problematic differing etch/mill rates associated with the differing materials. For example, in,
FIG. 1
, if it was desired to contact conductive wire
70
C, levels
140
,
130
,
120
,
110
,
110
,
90
, and
80
would need to be removed.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for vertically aligning fill shapes in several wiring levels in order to provide for line of sight views to lower wiring levels of the device.
This object of the invention is accomplished in a first method, by placing fill shapes on different wiring levels relative to a universal virtual grid. In a second method, fill shape placement is first performed on the highest wiring level requiring fill, and each lower wiring level is successively filled by aligning its fill shapes to those in the next higher wiring level.
It is a another object of the present invention to provide a method of making electrical taps to lower level conductive wires so they may be accessible from the top or near the top level of the device without having to delayer the device or at least minimize the amount of delayering.
This object of the invention is accomplished by connecting selected aligned fill shapes in several wiring levels with vias over the conductive wire to be tapped thus forming a conductive vertical stack. This stack is connected to the conductive wire by a via as well. In a first method, adjacent locations along a conductive wire are examined in sequence to see if aligned fill shapes exist in all higher levels above that location and as soon as one is found, the vias added. A second method is similar to the first, but differs in that aligned fill shapes are required as a prerequisite. In a third method, linking wires are used to connect selected conductive wires to the vertical conductive stack.
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Hartswick Thomas J.
Masters Mark E.
Everhart Caridad
Keshavan Belur V.
Walsh Robert A.
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