Method of designing and making an integrated circuit

Details Method of designing and making an integrated circuit Method of designing and making an integrated circuit

2005-12-13

2005-12-13

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06976232

ABSTRACT:
A method of transforming a first integrated circuit design comprising a plurality of D-type flip-flops each having a clock signal and being associated with an enable signal into a second integrated circuit design using guard-flops, the method comprising: identifying D-type flip-flops in the first integrated circuit design, and transforming each of the identified D-type flip-flops into a guard-flop comprising a transparent catch latch and a transparent pass latch; generating a catch enable signal for controlling the transparent catch latch from the clock signal and enable signal of the D-type flip-flop in the first integrated circuit design; and generating a pass enable signal for controlling the transparent pass latch based on the catch signals of at least some of the guard-flops that take data from the D-type flip-flop in the first integrated circuit design.

REFERENCES:
patent: 6038381 (2000-03-01), Munch et al.
patent: 6195786 (2001-02-01), Raghunathan et al.
patent: 2004/0006752 (2004-01-01), Whetsel
Surti et al., “Low Power FSM Design Using Huffman-Style Encoding”, Proceedings of European Design and Text Conference, Mar. 17, 1997, pp. 521-525.
Ecki et al., “Retiming Sequential Circuits With Multiple Register Classes”, Proceedings of Design, Automation and Test in Europe Conference and Exhibition, Mar. 9, 1999, pp. 650-656.
Guarded Evaluation: Pushing Power Management to Logic Synthesis/Design, V. Tiwari, S. Malik, P. Ashar, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17 iss 10, Oct. 1998, pp. 1-21.
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths, M. Munch, B. Wurth, R. Mehra, J. Sproch, N. When, Proceedings of the Design Automation and Test in Europe conference (DATE 2000), Mar. 2000, pp. 1-8.
Benini L. & Micheli G.D. “Synthesis of Low-Power Selectively-clocked Systems from High-Level Specification”ACM Transactions on Design Automation of Electronic Systems, vol. 5, No. 3, Jul. 2000, 311-321.
Benini et al. “Symbolic Synthesis of Clock-Gating Logic for Power Optimization of Synchronous Controllers” Association for Computing Machinery, Inc., Paper #L249, (C) 1998, 2000, pp. 1-24.
Raghavan et al. “Automatic Insertion of Gated Clocks at Register Transfer Level” Proceedings of the Twelfth International Conference on VLSI Design, 1999, 48-54.

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