Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-14
2004-02-17
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06694494
ABSTRACT:
FIELD AND BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit design and, more particularly, to an improved method of designing a single-chip integrated circuit that includes digital and/or analog and/or I/O and/or power and/or RF and/or electro-optical modules.
Methods of designing integrated chips that include only digital modules are well-known. See, for example, Dangelo et al., U.S. Pat. No. 6,216,252, which is incorporated by reference for all purposes as if fully set forth herein.
Methods of designing integrated chips that include both digital modules and analog, power, RF and/or electro-optical modules are less well established. The reason for this is historical. Although all electrical circuit designers once shared a common culture, this is no longer true.
The digital domain has taken the approach that a design engineer does not want to be bothered with the details. Current state of the art digital designers are really system-on-a chip designers, utilizing logic synthesis to create the desired systems. Little thought is given to how the library of logic blocks came to be or how many hours were spent characterizing the set-up and hold times. Digital designers just want the functionality to be exactly what is anticipated and for the timing to accurately reflect silicon.
Conversely, analog, power, RF and electro-optical engineers are from the old school: they don't trust what they didn't design themselves. Chances are that something in the specification has changed from the last time the module or function was used, and that change necessitates at least a review of the modules if not a complete re-design of the desired functions. Combining these two methodologies together to create a system-on-a-chip that includes digital, analog, power, RF and electro-optical functions is a complex task involving forethought and attention to detail.
One representative approach to the problem of combined digital-analog design can be found in Chang et al., U.S. Pat. No. 6,269,467, which is incorporated by reference for all purposes as if fully set forth herein.
One of the challenges in designing mixed-functionality integrated chips is that of preventing the signals in one type of block or module from interfering with the signals in another type of block or module. The three main mechanisms of unwanted interactions are through the substrate, through the power supplies and through the interconnects running between the various modules. In a typical design process, the modules are designed separately and then are laid out on the substrate. Then conductors for passing signals among the blocks are laid out either manually or using an automatic router. Guidelines are followed that allow as much isolation as possible between the various modules. An appropriate guardbar surrounding the analog-RF-electro-optical portion of the chip helps maintain the desired isolation.
Two general approaches are used in the layout of multi-signal circuits.
The first approach is to run separate power supplies to the different analog-RF-electro-optical and digital blocks. Ideally, the power supplies would come from separate power pins coming into the package with; separate traces running back to the power supply itself. If this is not possible, the next best option is to have separate supplies back to the power pad. This helps to isolate the noise coming through the metal power supply buses. This method of isolating power supplies is a general approach and is usually a good approach to multi-signal design regardless of what other methods are employed.
The second approach includes the separation of the power supplies and includes the isolation of the substrates to the extent possible. For example, in a standard CMOS process, the substrate is either bulk or epitaxial, and the isolation is most effectively done by guardbars and distance or proximity. A bulk substrate offers an advantage of additional resistance, acting as a filter to some of the high frequency noise that would otherwise affect surrounding circuitry. An epitaxial substrate is lower in resistance and therefore transmits noise signals more readily; but an epitaxial substrate offers better protection from latch up conditions and a slightly improved ESD (electrostatic discharge) protection over a bulk substrate.
The more area between the sensitive analog-RF-electro-optical portions of the circuit and the digital portions, the less interaction there is between the two groups. Guardbars are most effective next to the source of the noise and next to the circuitry being isolated. To further isolate the substrate, care must be taken to avoid injecting noise into the substrate. There are several mechanisms of noise injection. One way that noise is injected into the substrate is by overshooting the supply rails with input signals that are underdamped. These underdamped signals forward bias the PN junction diodes that make up the sources and drains of the transistors used in typical designs and inject current into the substrate. Overdamped signals may be just as damaging, not because of the substrate current and the associated noise, but because of the short circuit current and the associated noise on the power supply buses themselves. Often, separate supply buses are used to connect the substrate separately from the supplies carrying power to digital modules, to avoid the possibility of substrate noise being introduced by the relatively large noise spikes on the digital supplies.
In extreme cases, clock edges are slowed in order to reduce the noise introduced by the sudden transitions of the clock. Care must be taken in these cases to use modules that are accepting of slower clock edges and to make sure all the advantage gained by slower clock edges is not wasted because noise is introduced by the gates driven by the clock being in short circuit current mode for a longer period of time.
Outputs and inputs associated with the pads of the device also help in mixed signal design. Generally, a short, fat pad is preferred over the long, narrow pad associated with digital designs. This is generally true because few mixed signal circuits are pad limited. By having a shorter pad, the overall circuit size is smaller, which results in a cost savings. Most I/O pads for mixed signals now include multiple power supply buses that allow for multiple supply rails depending on the needs of the circuit. Often, the device is designed with a digital core and an analog-I/O ring. The digital core should be at a reduced voltage to help reduce power consumption, and the analog-I/O ring should be at a higher potential for interface and operational purposes. Often, an analog function is easier to realize with a higher supply voltage. As supply voltages decrease, some analog-RF-electro-optical techniques, such as cascaded devices, are not realizable.
Finally, as a mixed integrated circuit includes logic, memory, analog, electro-optical and RF modules, it must be possible to isolate any module for the purpose of testing. In other words, the inputs to the modules must be directly controllable from the chip inputs, and the outputs of the array must be directly observable at the chip output.
Although the prior art design methodology discussed above has been used successfully to integrate digital and analog modules on the same chip, the same can not be said for the integration of digital, RF and electro-optical modules on the same chip. This is particularly true with regard to chips implemented as silica-on-silicon, which is the most convenient technology for implementing electro-optical modules. There is thus a widely recognized need for, and it would be highly advantageous to have, a design method for a mixed-functionality integrated chip that allows the integration of digital, analog, RF and electro-optical modules on the same chip.
SUMMARY OF THE INVENTION
According to the present invention there is provided an improved method of designing a singe-chip circuit system that includes a first module and a second module dissimilar in type to the first module,
Daro Semiconductors Ltd.
Friedman Mark M.
Siek Vuthe
Tat Binh
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