Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-31
2010-10-26
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07823098
ABSTRACT:
A method of designing a digital circuit is described, so that it is likely to pass a signoff time test. The method begins with the running of a basic static time test on a partially developed version of the digital circuit, next a signoff time test is run for the partially developed version of the digital system. The differences between the results of the basic static time test and the signoff time test are noted and the prospective basic static time test passing conditions are altered so that if a similar system passes the basic static time test with the altered passing conditions it will be more likely to pass the signoff time test. Then, the partially developed version of the digital system is altered to yield a second partially developed version and the first static time test is run, with the altered passing conditions on the second partially developed version.
REFERENCES:
patent: 2005/0066297 (2005-03-01), Kalafala et al.
Donehue Paul J.
Gupta Puneet
Kahng Andrew B.
Moon Cho W.
Do Thuan
Martine & Penilla & Gencarella LLP
Tela Innovations, Inc.
LandOfFree
Method of designing a digital circuit by correlating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of designing a digital circuit by correlating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of designing a digital circuit by correlating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4183275